METHOD AND APPARATUS FOR PERFORMING CLOSE-LOOP PROGRAMMING OF RESISTIVE MEMORY DEVICES IN CROSSBAR ARRAY BASED HARDWARE CIRCUITS AND SYSTEMS
First Claim
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1. A method for programming neural networks having row and column arrays of resistive memory devices, said method comprising the steps of:
- initializing said resistive memory devices to a predetermined resistance value;
determining whether a training status tracker indicates that an overall training process is completed;
selecting a training pattern;
inputting said training pattern to said arrays and outputting a resulting signal;
detecting error by computing the difference between said output signal and an expected output signal value;
determining whether said detected error is within a near zero threshold and if so,updating said training progress in said training status tracker; and
returning to said step of determining whether said overall training process is completed;
otherwise, generating programming signals and adjusting resistance states of said resistive memory devices in said arrays by applying said programming signals;
resetting the training progress as in the status tracker; and
returning to said step of determining whether said overall training process is completed.
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Abstract
Method and apparatus for performing close-loop programming of resistive memory devices in crossbar array based hardware circuits and systems. Invention provides iterative training of memristor crossbar arrays for neural networks by applying voltages corresponding to selected training patterns. Error is detected and measured as a function of the actual response to the training patterns versus the expected response to the training pattern.
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Citations
28 Claims
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1. A method for programming neural networks having row and column arrays of resistive memory devices, said method comprising the steps of:
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initializing said resistive memory devices to a predetermined resistance value; determining whether a training status tracker indicates that an overall training process is completed; selecting a training pattern; inputting said training pattern to said arrays and outputting a resulting signal; detecting error by computing the difference between said output signal and an expected output signal value; determining whether said detected error is within a near zero threshold and if so, updating said training progress in said training status tracker; and returning to said step of determining whether said overall training process is completed; otherwise, generating programming signals and adjusting resistance states of said resistive memory devices in said arrays by applying said programming signals; resetting the training progress as in the status tracker; and returning to said step of determining whether said overall training process is completed. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. An apparatus for programming neural networks having row and column arrays of resistive memory devices, said apparatus comprising:
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a training status tracker (ST) for tracking overall training progress so as to keep record of training patterns to be excluded for a subsequent training pattern selection, and determining whether said overall training is completed; a read/write (R/W) control component that controls a recall and programming mode of a BSB recall circuit; a programming signal generator for generating signals to said arrays of resistive memory devices so as to adjust the resistance states of said resistive memory devices; an error detector for computing the difference between said training pattern input into said neural network and an output signal therefrom; an arbiter for determining whether said detected error is a vector of logic zero values and if so, said arbiter causes said status tracker to update training progress; and checks said status tracker to determine whether said overall training is completed; otherwise, said arbiter causes said programming signal generator to enable a programming mode of said arrays of resistive memory devices so as to adjust memristor resistance states; causes said status tracker to reset training progress; and checks said status tracker to determine whether said neural overall training is completed. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28)
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Specification