METHOD AND SYSTEM FOR PROGRAMMING A MULTI-BIT PER CELL NON-VOLATILE MEMORY

• US 20150170747A1
• Filed: 12/17/2013
• Published: 06/18/2015
• Est. Priority Date: 12/17/2013
• Status: Abandoned Application

• Current Assignee: Skymedi Corporation
• Original Assignee: Skymedi Corporation
• Inventors: Liu, Po-Yen, Chang, Che-Wei
• Application Number:
  US14/109,923
• Publication Number:
  US 20150170747A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/105 Circuits or methods for updating contents of nonvolatile memory, especially with 'security' features to ensure reliable replacement, i.e. preventing that old data is lost before new data is reliably written
• CPC Class Codes: G11C 16/107 Programming all cells in an array, sector or block to the same state prior to flash erasing
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

A system and method for programming a multi-bit per cell non-volatile memory with padding data is disclosed to program at least one less-significant-bit (LSB) page with padding data while programming host data in the multi-bit per cell non-volatile memory, in a manner such that a more-significant-bit (MSB) page corresponding to each LSB page programmed with host data of the same write command is programmed with host data.

Claims

1. A method for programming a multi-bit per cell non-volatile memory with padding data, comprising:

receiving a write command with host data; and

programming at least one less-significant-bit (LSB) page with padding data while programming the multi-bit per cell non-volatile memory with host data;

wherein the at least one LSB page is programmed in a manner such that a more-significant-bit (MSB) page corresponding to each LSB page programmed with host data of the same write command is programmed with host data.

2. The method of claim 1, wherein the multi-bit per cell non-volatile memory comprises a multi-bit per cell flash memory.

3. The method of claim 1, wherein the programming step comprises:

determining an LSB page number to denote an mount of the at least one LSB page programmed with padding data per write command, and a padding LSB page index to denote a beginning position of the at least one LSB page programmed with padding data per write command, according to information derived from the write command.

4. The method of claim 3, wherein the information of the write command comprises a length of the host data and a position of the host data.

5. The method of claim 1, wherein the at least one LSB page is programmed with dummy data.

6. The method of claim 1, wherein a portion of the at least one LSB page is programmed with old data to be garbage collected retrieved from the multi-bit per cell non-volatile memory.

7. The method of claim 1, further comprising:

receiving a stop write command; and

further programming at least one MSB page with padding data.

8. A system for programming a multi-bit per cell non-volatile memory with padding data, comprising:

a multi-bit per cell non-volatile memory; and

a controller disposed between a host and the multi-bit per cell non-volatile memory, the controller being configured to receive a write command with host data, and to program at least one less-significant-bit (LSB) page with padding data while programming the multi-bit per cell non-volatile memory with host data;

wherein the at least one LSB page is programmed in a manner such that an MSB page corresponding to each LSB page programmed with host data of the same write command is programmed with host data.

9. The system of claim 8, wherein the multi-bit per cell non-volatile memory comprises a multi-bit per cell flash memory.

10. The system of claim 8, wherein the controller comprises an interface electrically coupled to, and being communicating with, the host.

11. The system of claim 10, wherein the controller further comprises:

a buffer disposed between the interface and the multi-bit per cell non-volatile memory, the buffer being configured to temporarily store data while the data is being moved to or from the multi-bit per cell non-volatile memory.

12. The system of claim 8, wherein the controller comprises a dummy data generator configured to provide dummy data to be programming the at least one LSB page.

13. The system of claim 8, wherein the controller comprises an old data storage configured to store old data to be garbage collected retrieved from the multi-bit per cell non-volatile memory to be programming a portion of the at least one LSB page.