VARAINDUCTOR HAVING A SPIRAL INDUCTOR, VOLTAGE CONTROLLED OSCILLATOR INCLUDING THE VARAINDUCTOR, AND PHASE LOCKED LOOP INCLUDING THE VARAINDUCTOR

• US 20150170816A1
• Filed: 12/18/2013
• Published: 06/18/2015
• Est. Priority Date: 12/18/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: LIU, Yi-Hsuan, HSIEH, Hsieh-Hung, JOU, Chewn-Pu, HSUEH, Fu-Lung
• Granted Patent: US 9,478,344 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01F 2021/125 Printed variable inductor with taps, e.g. for VCO
• CPC Class Codes: H01F 21/12 discontinuously variable, e.g. tapped
• CPC Class Codes: H01F 27/2804 Printed windings
• CPC Class Codes: H01F 27/40 Structural association with built-in electric component, e.g. fuse
• CPC Class Codes: H01F 27/42 Circuits specially adapted for the purpose of modifying, or compensating for, electric characteristics of transformers, reactors, or choke coils circuits for controlling transformers, reactors or choke coils, for the purpose of obtaining a desired output H02P13/00; impedance networks H03H
• CPC Class Codes: H01F 29/02 with tappings on coil or winding; with provision for rearrangement or interconnection of windings
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/585 comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H03B 2201/0216 the means being an element with a variable inductance
• CPC Class Codes: H03B 5/1212 the amplifier comprising a pair of transistors, wherein an output terminal of each being connected to an input terminal of the other, e.g. a cross coupled pair
• CPC Class Codes: H03B 5/1228 the amplifier comprising one or more field effect transistors
• CPC Class Codes: H03B 5/1256 the means comprising a variable inductance
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop

Abstract

A varainductor includes a spiral inductor over a substrate, the spiral inductor comprising a ring portion. The varainductor further includes a ground ring over the substrate, the ground ring surrounding at least the ring portion of the spiral inductor and a floating ring over the substrate, the floating ring disposed between the ground ring and the spiral inductor. The varainductor further includes an array of switches, the array of switches is configured to selectively connect the ground ring to the floating ring.

Claims

1. A varainductor comprising:

a spiral inductor over a substrate, the spiral inductor comprising a ring portion;

a ground ring over the substrate, the ground ring surrounding at least the ring portion of the spiral inductor;

a floating ring over the substrate, the floating ring disposed between the ground ring and the spiral inductor; and

an array of switches, the array of switches is configured to selectively connect the ground ring to the floating ring.

2. The varainductor of claim 1, wherein each switch of the array of switches is configured to receive a same switch control signal.

3. The varainductor of claim 1, wherein at least one switch of the array of switches is configured to receive a different switch control signal from at least another switch of the array of switches.

4. The varainductor of claim 1, wherein the floating ring is located in a first tier of a monolithic three-dimensional integrated circuit (3DIC), the ground ring is located in a second tier of the monolithic 3DIC different from the first tier, and the floating ring is configured to be selectively connected to the ground ring through at least one inter-tier via.

5. The varainductor of claim 1, wherein the spiral inductor includes a first portion located a first distance from a top surface of the substrate, and a second portion located a second distance from the top surface of the substrate, and the first distance is different from the second distance.

6. The varainductor of claim 1, wherein at least one portion of the spiral inductor is located in a first tier of a monolithic three-dimensional integrated circuit (3DIC), at least one of the floating ring or the ground ring is located in a second tier of the monolithic 3DIC different from the first tier.

7. The varainductor of claim 1, wherein the array of switches includes at least one transistor, the at least one transistor is configured to selectively connect the floating ring located in a first tier of a monolithic three-dimensional integrated circuit (3DIC) to the ground ring located in a second tier of the monolithic 3DIC different from the first tier, and the at least one transistor is configured to selectively connect the floating ring to the ground ring through an inter-tier via.

8. The varainductor of claim 1, wherein the floating ring is spaced from the ground ring by a distance ranging from about 2 μ

m to about 50 μ

m.

9. The varainductor of claim 1, wherein the spiral inductor further comprises at least one input port and at least one output port

10. The varainductor of claim 1, wherein the floating ring is located in a same tier of a complementary metal oxide semiconductor (CMOS) circuit as the ground ring.

11. The varainductor of claim 9, wherein the at least one output port extends from the ring portion to a location outside the ground ring.

12. The varainductor of claim 11, wherein the array of switches comprises:

a first switch disposed on a first side of the spiral inductor; and

a second switch disposed on a second side of the spiral inductor opposite the first side.

13. An oscillator circuit comprising:

a first varainductor configured to receive a dc operating voltage and signal;

a second varainductor configured to receive the dc operating voltage and signal, wherein the second varainductor is electrically connected in parallel with the first varainductor;

a first transistor having a first terminal connected to the first varainductor; and

a second transistor having a first terminal connected to the second varainductor,

wherein at least one of the first varainductor or the second varainductor comprises a spiral inductor.

14. The oscillator circuit of claim 13, wherein at least one of the first varainductor or the second varainductor comprises:

the spiral inductor over a substrate, the spiral inductor comprising a ring portion;

a ground ring over the substrate, the ground ring surrounding at least the ring portion of the spiral inductor;

a floating ring over the substrate, the floating ring disposed between the ground ring and the spiral inductor; and

an array of switches, the array of switches is configured to selectively connect the ground ring to the floating ring.

15. The oscillator circuit of claim 14, wherein the oscillator circuit is a digital controlled oscillator (DCO), and at least one switch of the array of switches is configured to receive a different switch control signal from at least another switch of the array of switches.

16. The oscillator circuit of claim 14, wherein the floating ring is located in a first tier of a monolithic three-dimensional integrated circuit (3DIC), the ground ring is located in a second tier of the monolithic 3DIC different from the first tier, and the floating ring is configured to be selectively connected to the ground ring through at least one inter-tier via.

17. The oscillator circuit of claim 14, wherein the array of switches includes at least one transistor, the at least one transistor is configured to selectively connect the floating ring located in a first tier of a monolithic three-dimensional integrated circuit (3DIC) to the ground ring located in a second tier of the monolithic 3DIC different from the first tier, and the at least one transistor is configured to selectively connect the floating ring to the ground ring through an inter-tier via.

18. A phase locked loop (PLL) comprising:

a phase frequency detector (PFD) configured to receive a reference frequency and a feedback frequency, the PFD configured to generate a first control signal;

a charge pump (CP) configured to receive the first control signal and generate an analog voltage signal;

a low pass filter (LPF) configured to receive the analog voltage signal and generate a second control signal;

an oscillator circuit configured to receive the second control signal and generate and output signal, the oscillator circuit comprising;

a first varainductor configured to receive an operating voltage;

a second varainductor configured to receive the operating voltage, wherein the second varainductor is electrically connected in parallel with the first varainductor;

a first transistor having a first terminal connected to the first varainductor; and

a second transistor having a first terminal connected to the second varainductor,

wherein at least one of the first varainductor or the second varainductor comprises a spiral inductor; and

a frequency divider (FD) configured to receive the output signal and generate the feedback frequency.

19. The PLL of claim 18, wherein at least one of the first varainductor or the second varainductor comprises:

a spiral inductor over a substrate, the spiral inductor comprising a ring portion;

a ground ring over the substrate, the ground ring surrounding at least the ring portion of the spiral inductor;

a floating ring over the substrate, the floating ring disposed between the ground ring and the spiral inductor; and

an array of switches, the array of switches is configured to selectively connect the ground ring to the floating ring.

20. The PLL of claim 19, wherein the floating ring is located in a first tier of a monolithic three-dimensional integrated circuit (3DIC), the ground ring is located in a second tier of the monolithic 3DIC different from the first tier, and the floating ring is configured to be selectively connected to the ground ring through at least one inter-tier via.