SEMICONDUCTOR DEVICE

• US 20150170980A1
• Filed: 09/10/2014
• Published: 06/18/2015
• Est. Priority Date: 12/13/2013
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Yamazaki, Takashi, Kosaka, Yoshiyuki
• Application Number:
  US14/482,438
• Publication Number:
  US 20150170980A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48095 Kinked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06562 at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49805 the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

A semiconductor device of embodiment includes: a wiring substrate having a first surface, a second surface and a side surface; a semiconductor element mounted on the first surface; a sealing resin layer sealing the semiconductor element and the first surface; a conductive shield layer covering the sealing resin layer and the side surface; and plural vias. At least one via is electrically connected to the conductive shield layer, and the plural vias are each arranged along peripheral part of the wiring substrate. When plural predetermined vias arranged at one side part of the peripheral part of the wiring substrate are seen through thickness direction of the wiring substrate, width of area totally occupied by the plural predetermined vias in direction perpendicular to the side part is larger than width an area occupied by each of the predetermined vias as a single via in direction along the side part.

Claims

1. A semiconductor device, comprising:

a wiring substrate having a first surface, a second surface and a side surface,

a semiconductor element mounted on the first surface;

a sealing resin layer sealing the semiconductor element and the first surface;

a conductive shield layer covering the sealing resin layer and the side surface; and

plural vias each arranged along a peripheral part of the wiring substrate, at least one of the vias being electrically connected to the conductive shield layer,

wherein when plural predetermined vias arranged at one side part of the peripheral part of the wiring substrate from among the plural vias are seen through a thickness direction of the wiring substrate, a width of an area totally occupied by the plural predetermined vias in a direction perpendicular to the side part is larger than a width of an area occupied by each of the predetermined vias as a single via in a direction along the side part.

2. The semiconductor device of claim 1,

wherein, when the plural predetermined vias are seen through the thickness direction of the wiring substrate, at least one of the plural predetermined vias is disposed while being shifted in a direction perpendicular to the side part relative to the other predetermined vias.

3. The semiconductor device of claim 1,

wherein, when the plural predetermined vias are seen through the thickness direction of the wiring substrate, an aspect ratio of a shape of each of the predetermined vias is different.

4. The semiconductor device of claim 2,

wherein, when the plural predetermined vias are seen through the thickness direction of the wiring substrate, an aspect ratio of a shape of each of the predetermined vias is different.

5. The semiconductor device of claim 1,

wherein, when the plural predetermined vias are seen through a direction along the first surface, a portion formed at the first surface side by each of the predetermined vias and a portion formed at the second surface side by each of the predetermined vias are disposed while being relatively shifted in the direction perpendicular to the side part.

6. The semiconductor device of claim 2,

wherein, when the plural predetermined vias are seen through a direction along the first surface, a portion formed at the first surface side by each of the predetermined vias and a portion formed at the second surface side by each of the predetermined vias are disposed while being relatively shifted in the direction perpendicular to the side part.

7. The semiconductor device of claim 3,

wherein, when the plural predetermined vias are seen through a direction along the first surface, a portion formed at the first surface side by each of the predetermined vias and a portion formed at the second surface side by each of the predetermined vias are disposed while being relatively shifted in the direction perpendicular to the side part.

8. The semiconductor device of claim 4,

wherein, when the plural predetermined vias are seen through a direction along the first surface, a portion formed at the first surface side by each of the predetermined vias and a portion formed at the second surface side by each of the predetermined vias are disposed while being relatively shifted in the direction perpendicular to the side part.

9. The semiconductor device of claim 5,

wherein, the wiring substrate is a multilayer board of three layers or more, and

each of the plural predetermined vias is a stacked via.

10. The semiconductor device of claim 6,

wherein the wiring substrate is a multilayer board of three layers or more, and each of the plural predetermined vias is a stacked via.

11. The semiconductor device of claim 7,

wherein the wiring substrate is a multilayer board of three layers or more, and each of the plural predetermined vias is a stacked via.

12. The semiconductor device of claim 8,

wherein the wiring substrate is a multilayer board of three layers or more, and each of the plural predetermined vias is a stacked via.

13. The semiconductor device of claim 1,

wherein the plural predetermined vias are each connected to ground wirings, and at least one of the plural predetermined vias is exposed to the side surface, and is electrically connected to the conductive shield layer via the exposed side surface.

14. The semiconductor device of claim 2,

wherein the plural predetermined vias are each connected to ground wirings, and at least one of the plural predetermined vias is exposed to the side surface, and is electrically connected to the conductive shield layer via the exposed side surface.

15. The semiconductor device of claim 3,

wherein the plural predetermined vias are each connected to ground wirings, and at least one of the plural predetermined vias is exposed to the side surface, and is electrically connected to the conductive shield layer via the exposed side surface.

16. The semiconductor device of claim 4,

wherein the plural predetermined vias are each connected to ground wirings, and at least one of the plural predetermined vias is exposed to the side surface, and is electrically connected to the conductive shield layer via the exposed side surface.

17. The semiconductor device of claim 1, further comprising:

a first pad used for a resistance value measurement provided at the second surface side, the first pad being electrically connected to the conductive shield layer; and

a second pad used for the resistance value measurement provided at the second surface side, the second pad constituting a mark for alignment of the wiring substrate, the second pad being electrically connected to the conductive shield layer.

18. The semiconductor device of claim 2, further comprising:

a first pad used for a resistance value measurement provided at the second surface side, the first pad being electrically connected to the conductive shield layer; and

a second pad used for the resistance value measurement provided at the second surface side, the second pad constituting a mark for alignment of the wiring substrate, the second pad being electrically connected to the conductive shield layer.

19. The semiconductor device of claim 3, further comprising:

a first pad used for a resistance value measurement provided at the second surface side, the first pad being electrically connected to the conductive shield layer; and

a second pad used for the resistance value measurement provided at the second surface side, the second pad constituting a mark for alignment of the wiring substrate, the second pad being electrically connected to the conductive shield layer.

20. The semiconductor device of claim 4, further comprising:

a first pad used for a resistance value measurement provided at the second surface side, the first pad being electrically connected to the conductive shield layer; and

a second pad used for the resistance value measurement provided at the second surface side, the second pad constituting a mark for alignment of the wiring substrate, the second pad being electrically connected to the conductive shield layer.