ION SENSITIVE FIELD EFFECT TRANSISTORS WITH PROTECTION DIODES AND METHODS OF THEIR FABRICATION

• US 20150171018A1
• Filed: 12/18/2013
• Published: 06/18/2015
• Est. Priority Date: 12/18/2013
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Md M. Hoque, Patrice Parris, Weize Chen
• Inventors: HOQUE, MD M., CHEN, WEIZE, PARRIS, PATRICE, DE SOUZA, RICHARD
• Granted Patent: US 9,978,689 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G01N 27/414 Ion-sensitive or chemical field-effect transistors, i.e. ISFETS or CHEMFETS
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An embodiment of an Ion Sensitive Field Effect Transistor (ISFET) structure includes a substrate, source and drain regions formed within the substrate and spatially separated by a channel region, a gate dielectric and a gate formed over the channel region, multiple conductive structures overlying the surface of the substrate, and one or more protection diode circuits coupled between one or more of the multiple conductive structures and the substrate. The multiple conductive structures include a floating gate structure and a sense plate structure. The floating gate structure is formed over the gate dielectric and includes the gate. The sense plate structure is electrically coupled to the floating gate structure and is configured to sense a concentration of a target ion or molecule in a fluid adjacent to a portion of the sense plate structure.

Claims

1. An Ion Sensitive Field Effect Transistor (ISFET) structure comprising:

a substrate having a surface;

a source region and a drain region formed within the substrate and spatially separated across the surface of the substrate by a channel region;

a gate dielectric formed on the surface of the substrate over the channel region;

a gate formed on the gate dielectric;

multiple conductive structures overlying the surface of the substrate, wherein the multiple conductive structures include

a floating gate structure formed over the gate dielectric and including the gate, and

a sense plate structure electrically coupled to the floating gate structure and configured to sense a concentration of a target ion or molecule in a fluid adjacent to a portion of the sense plate structure; and

a first protection diode circuit coupled between one of the multiple conductive structures and the substrate.

2. The ISFET structure of claim 1, wherein the first protection diode circuit comprises at least one PN junction between a first set of adjacent regions of opposite conductivity type formed within the substrate.

3. The ISFET structure of claim 2, wherein the first protection diode circuit is coupled to the floating gate structure, and wherein the ISFET structure further comprises:

a second protection diode circuit coupled to the sense plate structure, wherein the second protection diode circuit comprises at least one second PN junction between a second set of adjacent regions of opposite conductivity type formed within the substrate.

4. The ISFET structure of claim 2, wherein:

the substrate includes a first region of a first conductivity type that extends to the surface of the substrate;

the source region and the drain region are regions of a second conductivity type formed within the first region; and

the first protection diode circuit comprises a second region of the second conductivity type formed within the first region, wherein the at least one PN junction includes a PN junction formed between the first region and the second region.

5. The ISFET structure of claim 2, wherein:

the substrate includes a first region of a first conductivity type that extends to the surface of the substrate;

the source region and the drain region are regions of a second conductivity type formed within the first region; and

the first protection diode circuit comprises

a first well region of the second conductivity type formed within the first region;

a second well region of the first conductivity type formed within the first well region;

a second region of the second conductivity type formed within the second well region, wherein the at least one PN junction includes a first PN junction formed between the first region and the first well region, a second PN junction formed between the first well region and the second well region, and a third PN junction formed between the second well region and the second region.

6. The ISFET structure of claim 5, wherein the first protection diode circuit further comprises:

a third region of the first conductivity type formed within the second well region, and wherein the ISFET structure further comprises;

a contact coupled to the third region and configured to receive a voltage to bias the second well region.

7. The ISFET structure of claim 1, wherein the sense plate structure comprises:

a conductive sense plate formed from a first metal layer proximate a surface of the ISFET structure;

a first metal conductor formed in a second metal layer underlying the first metal layer; and

at least one conductive via electrically coupling the first metal conductor and the sense plate.

8. The ISFET structure of claim 7, wherein the floating gate structure comprises:

the gate formed on the gate dielectric;

a second metal conductor formed in a third metal layer underlying the second metal layer; and

at least one conductive via electrically coupling the second metal conductor and the gate.

9. The ISFET structure of claim 8, further comprising:

an oxide layer formed between the first and second metal conductors, wherein the first and second metal conductors and the oxide layer function to capacitively couple the sense plate structure and the floating gate structure.

10. The ISFET structure of claim 8, wherein the gate is a polysilicon gate.

11. The ISFET structure of claim 1, further comprising:

at least one control gate structure electrically coupled to the floating gate structure, the control gate structure configured to accept a voltage bias and to cause the movement of charge between the floating gate structure and the control gate structure in response to the voltage bias.

12. An Ion Sensitive Field Effect Transistor (ISFET) structure comprising:

a substrate having a surface;

a source region and a drain region formed within the substrate and spatially separated across the surface of the substrate by a channel region;

a gate dielectric formed on the surface of the substrate over the channel region;

a gate formed on the gate dielectric;

a floating gate structure formed over the gate dielectric and including the gate;

a sense plate structure electrically coupled to the floating gate structure and configured to sense a concentration of a target ion or molecule in a fluid adjacent to a portion of the sense plate structure; and

a first protection diode circuit coupled between the floating gate structure and the substrate, wherein the first protection diode circuit comprises at least one PN junction between a first set of adjacent regions of opposite conductivity type formed within the substrate.

13. The ISFET structure of claim 12, further comprising:

a second protection diode circuit coupled to the sense plate structure, wherein the second protection diode circuit comprises at least one second PN junction between a second set of adjacent regions of opposite conductivity type formed within the substrate.

14. The ISFET structure of claim 12, wherein:

the substrate includes a first region of a first conductivity type that extends to the surface of the substrate;

the source region and the drain region are regions of a second conductivity type formed within the first region; and

the first protection diode circuit comprises a second region of the second conductivity type formed within the first region, wherein the at least one PN junction includes a PN junction formed between the first region and the second region.

15. The ISFET structure of claim 12, wherein:

the substrate includes a first region of a first conductivity type that extends to the surface of the substrate;

the source region and the drain region are regions of a second conductivity type formed within the first region; and

the first protection diode circuit comprises

a first well region of the second conductivity type formed within the first region,

a second well region of the first conductivity type formed within the first well region,

a second region of the second conductivity type formed within the second well region, wherein the at least one PN junction includes a first PN junction formed between the first region and the first well region, a second PN junction formed between the first well region and the second well region, and a third PN junction formed between the second well region and the second region.

16. The ISFET structure of claim 15, wherein the first protection diode circuit further comprises:

a third region of the first conductivity type formed within the second well region, and wherein the ISFET structure further comprises;

a contact coupled to the third region and configured to receive a voltage to bias the second well region.

17. A method of fabricating an Ion Sensitive Field Effect Transistor (ISFET) structure, the method comprising the steps of:

forming a gate dielectric and a gate on a surface of a substrate over a channel region;

forming a source region and a drain region within the substrate, wherein the source region and the drain region are spatially separated across the surface of the substrate by the channel region;

forming a first protection diode circuit;

forming multiple conductive structures overlying the surface of the substrate, wherein the multiple conductive structures include

a floating gate structure coupled to and including the gate, and

a sense plate structure electrically coupled to the floating gate structure and configured to sense a concentration of a target ion or molecule in a fluid adjacent to a portion of the sense plate structure; and

electrically connecting the first protection diode circuit to one of the multiple conductive structures.

18. The method of fabricating an ISFET structure of claim 17, wherein forming the first protection diode circuit includes forming at least one PN junction between a first set of adjacent regions of opposite conductivity type formed within the substrate.

19. The method of fabricating an ISFET structure of claim 18, further comprising:

forming a second protection diode circuit, wherein the second protection diode circuit includes at least one second PN junction between a second set of adjacent regions of opposite conductivity type formed within the substrate; and

electrically connecting the second protection diode circuit to another one of the multiple conductive structures.

20. The method of fabricating an ISFET structure of claim 18, wherein:

the substrate includes a first region of a first conductivity type that extends to the surface of the substrate;

forming the source region and the drain region comprises forming source and drain regions of a second conductivity type within the first region; and

forming the first protection diode circuit comprises forming a second region of the second conductivity type within the first region, wherein the at least one PN junction includes a PN junction formed between the first region and the second region.

21. The method of fabricating an ISFET structure of claim 18, wherein:

the substrate includes a first region of a first conductivity type that extends to the surface of the substrate;

forming the source region and the drain region comprises forming source and drain regions of a second conductivity type within the first region; and

forming the first protection diode circuit comprises

forming a first well region of the second conductivity type within the first region,

forming a second well region of the first conductivity type within the first well region, and

forming a second region of the second conductivity type within the second well region, wherein the at least one PN junction includes a first PN junction formed between the first region and the first well region, a second PN junction formed between the first well region and the second well region, and a third PN junction formed between the second well region and the second region.

22. The method of fabricating an ISFET structure of claim 21, wherein:

forming the first protection diode circuit further comprises forming a third region of the second conductivity type within the second well region; and

fabricating the ISFET structure further comprises;

electrically coupling a contact to the third region, wherein the contact is configured to receive a voltage to bias the second well region.