VERTICAL NANOWIRE TRANSISTOR FOR INPUT/OUTPUT STRUCTURE

• US 20150171032A1
• Filed: 12/18/2013
• Published: 06/18/2015
• Est. Priority Date: 12/18/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Colinge, Jean-Pierre, Diaz, Carlos H., Guo, Ta-Pen
• Granted Patent: US 9,177,924 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Systems for protecting a circuit from an electrostatic discharge (ESD) voltage are provided. An input terminal receives an input signal. An ESD protection circuit receives the input signal from the input terminal. The ESD protection circuit includes one or more vertical nanowire field effect transistors (FETs). Each of the one or more vertical nanowire FETs includes a well of a first conductivity type. Each of the one or more vertical nanowire FETs also includes a nanowire having i) a source region at a first end of the nanowire, and ii) a drain region at a second end of the nanowire that is opposite the first end. The source region further includes a portion formed in the well, where the source region and the drain region are of a second conductivity type. A gate region surrounds a portion of the nanowire and is separated from the drain region by a distance.

Claims

1. A system for protecting a circuit from an electrostatic discharge (ESD) voltage, the system comprising:

an input terminal for receiving an input signal;

an ESD protection circuit configured to receive the input signal from the input terminal, the ESD protection circuit including one or more vertical nanowire field effect transistors (FETs), wherein each of the one or more vertical nanowire FETs includes;

a well of a first conductivity type that is formed in a semiconductor substrate,

a nanowire having i) a source region at a first end of the nanowire, and ii) a drain region at a second end of the nanowire that is opposite the first end, the source region further including a portion formed in the well, wherein the source region and the drain region are of a second conductivity type such that a PN junction is formed between the well and the portion of the source region formed in the well, and

a gate region surrounding a portion of the nanowire, wherein the gate region is separated from the drain region by a first distance, the separation of the gate region and the drain region providing a resistance in series between the drain region and the source region; and

an output terminal configured to receive the input signal from the ESD protection circuit, wherein an ESD-induced voltage in the input signal is attenuated by the resistance and the PN junction.

2. The system of claim 1, wherein a second circuit is coupled to the output terminal, and wherein the second circuit is protected from the ESD-induced voltage.

3. The system of claim 2, wherein the input terminal, the ESD protection circuit, the output terminal, and the second circuit comprise portions of an integrated circuit, wherein the second circuit includes one or more core transistors that implement a logical design for the integrated circuit, and wherein the one or more vertical nanowire FETs of the ESD protection circuit are input/output transistors for the integrated circuit.

4. The system of claim 3, wherein a same type of vertical nanowire FET is used for the one or more core transistors and for the input/output transistors.

5. The system of claim 1, wherein the one or more vertical nanowire FETs are junctionless accumulation-mode nanowire transistors.

6. The system of claim 1, wherein the gate region includes a gate dielectric, and wherein the resistance reduces an electric field in the gate dielectric.

7. The system of claim 1, wherein the ESD protection circuit includes:

a PMOS vertical nanowire FET, the PMOS vertical nanowire FET including an N-type well, a P-type source region, and a P-type drain region; and

an NMOS vertical nanowire FET, the NMOS vertical nanowire FET including a P-type well, an N-type source region, and an N-type drain region,

wherein the PMOS vertical nanowire FET and the NMOS vertical nanowire FET are connected in an electrically parallel arrangement.

8. The system of claim 7, wherein the input terminal is connected to the drain region of the PMOS vertical nanowire FET and the drain region of the NMOS vertical nanowire FET, and the output terminal is connected to the source region of the PMOS vertical nanowire FET and the source region of the NMOS vertical nanowire FET.

9. The system of claim 8, wherein a first path between the input terminal and the output terminal includes the resistance in series between the drain and source regions of the PMOS vertical nanowire FET, and wherein a second path between the input terminal and the output terminal includes the resistance in series between the drain and source regions of the NMOS vertical nanowire FET.

10. The system of claim 8, wherein a ground reference voltage is applied to one of the PMOS vertical nanowire FET or the NMOS vertical nanowire FET, wherein a VDD reference voltage is applied to the other of the PMOS vertical nanowire FET or the NMOS vertical nanowire FET, and wherein the PN junctions of the PMOS and NMOS vertical nanowire FETs clamp a voltage at the output terminal between the ground reference voltage and the VDD reference voltage.

11. The system of claim 10, wherein the ground reference voltage is applied to the P-type well of the NMOS vertical nanowire FET, and wherein the VDD reference voltage is applied to the N-type well of the PMOS vertical nanowire FET.

12. The system of claim 8, wherein the ESD protection circuit further includes:

a second PMOS vertical nanowire FET, the second PMOS vertical nanowire FET including a second N-type well, a second P-type source region, and a second P-type drain region; and

a second NMOS vertical nanowire FET, the second NMOS vertical nanowire FET including a second P-type well, a second N-type source region, and a second N-type drain region,

wherein the input terminal is connected to i) the second P-type source region of the second PMOS vertical nanowire FET, and ii) the second N-type source region of the second NMOS vertical nanowire FET.

13. The system of claim 12, wherein a ground reference voltage is applied to one of the second PMOS vertical nanowire FET or the second NMOS vertical nanowire FET, wherein a VDD reference voltage is applied to the other of the second PMOS vertical nanowire FET or the second NMOS vertical nanowire FET, and wherein the PN junctions of the second PMOS and the second NMOS vertical nanowire FETs clamp a voltage at the input terminal between the ground reference voltage and the VDD reference voltage.

14. The system of claim 13, wherein the ground reference voltage is applied to the second P-type well of the second NMOS vertical nanowire FET, and wherein the VDD reference voltage is applied to the second N-type well of the second PMOS vertical nanowire FET.

15. A system for protecting a circuit from an electrostatic discharge (ESD) voltage, the system comprising:

an input terminal for receiving an input signal;

a semiconductor substrate including a first well region and a second well region, wherein the first well region is of a first conductivity type, and the second well region is of a second conductivity type;

an ESD protection circuit configured to receive the input signal from the input terminal, the ESD protection circuit including;

a first vertical nanowire field effect transistor (FET), wherein a first PN junction is formed between the first well region and a source or drain region of the first vertical nanowire FET, and

a second vertical nanowire FET, wherein a second PN junction is formed between the second well region and a source or drain region of the second vertical nanowire FET; and

an output terminal configured to receive the input signal from the ESD protection circuit.

16. The system of claim 15, wherein the input terminal is connected to the source region of the first vertical nanowire FET and the source region of the second vertical nanowire FET, wherein the output terminal is connected to the source region of the first vertical nanowire FET and the source region of the second vertical nanowire FET, wherein a ground reference voltage is coupled to the first PN junction, wherein a VDD reference voltage is coupled to the second PN junction, and wherein the first and second PN junctions clamp a voltage at the input terminal between the ground reference voltage and the VDD reference voltage.

17. The system of claim 15,

wherein the first vertical nanowire FET is a PMOS vertical nanowire FET, the PMOS vertical nanowire FET including an N-type well, a P-type source region, a P-type drain region, and a first gate region;

and

wherein the second vertical nanowire FET is an NMOS vertical nanowire FET, the NMOS vertical nanowire FET including a P-type well, an N-type source region, an N-type drain region, and a second gate region,

wherein a ground reference voltage is applied to the P-type well and the N-type drain region of the NMOS vertical nanowire FET,

wherein a VDD reference voltage is applied to the N-type well and the P-type drain region of the PMOS vertical nanowire FET,

wherein the input terminal is connected to the first gate region and the second gate region,

wherein the output terminal is connected to the P-type source region of the PMOS vertical nanowire FET and to the N-type source region of the NMOS vertical nanowire FET, and

wherein the first and second PN junctions clamp a voltage at the output terminal between the ground reference voltage and the VDD reference voltage.

18. The system of claim 15,

wherein the first vertical nanowire FET includes a first gate region that is separated from the source or drain region of the first vertical nanowire FET by a first distance,

wherein the second vertical nanowire FET includes a second gate region that is separated from the source or drain region of the second vertical nanowire FET by a second distance, and

wherein the first distance and the second distance attenuate the ESD-induced voltage by lowering an electric field in the first and second gate regions.

19. The system of claim 15, wherein a second circuit is coupled to the output terminal, and wherein the second circuit is protected from the ESD-induced voltage.

20. A system for protecting a circuit from an electrostatic discharge (ESD) voltage, the system comprising:

an input terminal for receiving an input signal;

an ESD protection circuit configured to receive the input signal from the input terminal, the ESD protection circuit including one or more vertical nanowire field effect transistors (FETs), wherein each of the one or more vertical nanowire FETs includes;

a well of a first conductivity type that is formed in a semiconductor substrate,

a nanowire having i) a drain region at a first end of the nanowire, and ii) a source region at a second end of the nanowire that is opposite the first end, the drain region further including a portion formed in the well, wherein the drain region and the source region are of a second conductivity type such that a PN junction is formed between the well and the portion of the drain region formed in the well, and

a gate region surrounding a portion of the nanowire, wherein the gate region is separated from the source region by a first distance, the separation of the gate region and the source region providing a resistance in series between the source region and the drain region; and

an output terminal configured to receive the input signal from the ESD protection circuit, wherein an ESD-induced voltage in the input signal is attenuated by the resistance and the PN junction.