ANTIFUSE

• US 20150171094A1
• Filed: 07/04/2013
• Published: 06/18/2015
• Est. Priority Date: 07/10/2012
• Status: Active Grant

• Current Assignee: Soitec S.A.
• Original Assignee: Soitec S.A.
• Inventors: Hofmann, Franz
• Granted Patent: US 10,186,515 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 27/101 including resistors or capacitors only
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 20/20 Programmable ROM [PROM] devices comprising field-effect components H10B20/10 takes precedence
• CPC Class Codes: H10B 20/60 Peripheral circuit regions

Abstract

The disclosure relates to a semiconductor structure comprising: a first semiconductor layer, a first program transistor, and a first select transistor implementing a first antifuse cell, wherein the first semiconductor layer acts as the body of the first program transistor and as the body of the first select transistor, wherein a gate of the first program transistor and a gate of the first select transistor are on different sides of the first semiconductor layer.

Claims

1. A semiconductor structure, comprising:

a first semiconductor layer; and

a first program transistor and a first select transistor implementing a first antifuse cell, wherein the first semiconductor layer acts as the body of the first program transistor and as the body of the first select transistor;

wherein a gate of the first program transistor and a gate of the first select transistor are on different sides of the first semiconductor layer.

2. The semiconductor structure according to claim 1, wherein the semiconductor structure is a multi-gate semiconductor structure, and the gate of the first program transistor and the gate of the first select transistor are, respectively, one a back-gate and one a top-gate, or vice versa, of the multi-gate semiconductor structure.

3. The semiconductor structure according to claim 2, further comprising:

at least one second program transistor implementing a second antifuse cell in combination with the first select transistor, wherein the first program transistor is connected in parallel with the at least one second program transistor.

4. The semiconductor structure according to claim 3, further comprising:

at least one third program transistor implementing a third antifuse cell in combination with the first select transistor, wherein the first program transistor is connected in series with the at least one third program transistor.

5. The semiconductor structure according to claim 4, wherein the gate and gate oxide of any of the program transistors are shaped such that the electric field of the gate is concentrated on a point or a line of the gate oxide.

6. The semiconductor structure according to claim 5, wherein:

the first semiconductor layer comprises an etched region;

the gate oxide is placed on the first semiconductor layer and at least on a portion of the wall of the etched region; and

the gate is placed on the gate oxide, so as to realize an angle in correspondence of the etched region.

7. The semiconductor structure according to claim 1, further comprising:

at least one second program transistor implementing a second antifuse cell in combination with the first select transistor, wherein the first program transistor is connected in parallel with the at least one second program transistor.

8. The semiconductor structure according to claim 7, further comprising:

at least one third program transistor implementing a third antifuse cell in combination with the first select transistor, wherein the first program transistor is connected in series with the at least one third program transistor.

9. The semiconductor structure according to claim 1, wherein the gate and gate oxide of any of the program transistors are shaped such that the electric field of the gate is concentrated on a point or a line of the gate oxide.

10. The semiconductor structure according to claim 2, wherein the gate and gate oxide of any of the program transistors are shaped such that the electric field of the gate is concentrated on a point or a line of the gate oxide.

11. The semiconductor structure according to claim 10, wherein:

the first semiconductor layer comprises an etched region;

the gate oxide is placed on the first semiconductor layer and at least on a portion of the wall of the etched region; and

the gate is placed on the gate oxide, so as to realize an angle in correspondence of the etched region.

12. The semiconductor structure according to claim 1, wherein the gate of the first program transistor and the gate of the first select transistor are on opposite sides of the first semiconductor layer.

13. The semiconductor structure according to claim 1, further comprising a second program transistor, and wherein the first program transistor, the second program transistor, and the first select transistor implement a NOR antifuse cell arrangement.

14. The semiconductor structure according to claim 1, further comprising a second program transistor, and wherein the first program transistor, the second program transistor, and the first select transistor implement a NAND antifuse cell arrangement.