SEMICONDUCTOR DEVICE

• US 20150171115A1
• Filed: 12/09/2014
• Published: 06/18/2015
• Est. Priority Date: 12/12/2013
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: YAMAZAKI, Shunpei, OKAZAKI, Kenichi, KATAYAMA, Masahiro
• Granted Patent: US 9,349,751 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G02F 1/133345 Insulating layers G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence
• CPC Class Codes: G02F 1/133553 Reflecting elements associated to illuminating devices G02F1/133605
• CPC Class Codes: G02F 1/1337 Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
• CPC Class Codes: G02F 1/1339 Gaskets; Spacers; Sealing of cells
• CPC Class Codes: G02F 1/13439 characterised by their electrical, optical, physical properties; materials therefor; method of making
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76861 Post-treatment or after-treatment not introducing additional chemical elements into the layer
• CPC Class Codes: H01L 23/373 Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1251 comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• CPC Class Codes: H10K 59/121 : characterised by the geometry or disposition of pixel elements

Abstract

A semiconductor device provided with a plurality of kinds of transistors with different device structures suitable for functions of circuits is provided. The semiconductor device includes first to third transistors with different device structures over one substrate. A semiconductor layer of the first transistor is an oxide semiconductor film with a stacked-layer structure, and a semiconductor layer of each of the second and third transistors is an oxide semiconductor film with a single-layer structure. Each of the first and second transistors includes a back gate electrode connected to its gate electrode.

Claims

1. A semiconductor device comprising:

a first circuit comprising a first transistor and a second transistor over a substrate; and

a second circuit comprising a third transistor over the substrate;

wherein the first transistor comprises a first oxide semiconductor film, a second oxide semiconductor film and a first gate electrode, the first gate electrode overlapping with the first oxide semiconductor film and the second oxide semiconductor film,

wherein the second transistor comprises a third oxide semiconductor film,

wherein the third transistor comprises a fourth oxide semiconductor film,

wherein the second oxide semiconductor film, the third oxide semiconductor film and the fourth oxide semiconductor film comprise a same material, and

wherein the first transistor comprises a first back gate electrode connected to the first gate electrode.

2. The semiconductor device according to claim 1, wherein a channel length of the first transistor is less than 2.5 μ

m.

3. The semiconductor device according to claim 1, wherein the second transistor further comprises a second gate electrode overlapping with the third oxide semiconductor film and a second back gate electrode connected to the second gate electrode.

4. The semiconductor device according to claim 1, further comprising:

a pixel portion that comprises the second circuit; and

a driver circuit that drives the pixel portion and comprises the first circuit.

5. The semiconductor device according to claim 1, wherein a top surface and a side surface of the first oxide semiconductor film are covered with the second oxide semiconductor film.

6. The semiconductor device according to claim 1, wherein a field-effect mobility of the first transistor is greater than a field-effect mobility of the third transistor.

7. The semiconductor device according to claim 1, wherein the second oxide semiconductor film, the third oxide semiconductor film and the fourth oxide semiconductor film are formed in a same step.

8. An electronic device comprising the semiconductor device according to claim 1.

9. A semiconductor device comprising:

a first circuit comprising a first transistor and a second transistor over a substrate; and

a second circuit comprising a third transistor over the substrate;

wherein the first transistor comprises a first oxide semiconductor film, a second oxide semiconductor film and a third oxide semiconductor film stacked in this order and a first gate electrode, the first gate electrode overlapping with the first oxide semiconductor film, the second oxide semiconductor film and the third oxide semiconductor film,

wherein the second transistor comprises a fourth oxide semiconductor film,

wherein the third transistor comprises a fifth oxide semiconductor film,

wherein the third oxide semiconductor film, the fourth oxide semiconductor film and the fifth oxide semiconductor film comprise a same material, and

wherein the first transistor comprises a first back gate electrode connected to the first gate electrode.

10. The semiconductor device according to claim 9, wherein a channel length of the first transistor is less than 2.5 μ

m.

11. The semiconductor device according to claim 9, wherein the second transistor further comprises a second gate electrode overlapping with the fourth oxide semiconductor film and a second back gate electrode connected to the second gate electrode.

12. The semiconductor device according to claim 9, further comprising:

a pixel portion that comprises the second circuit; and

a driver circuit that drives the pixel portion and comprises the first circuit.

13. The semiconductor device according to claim 9, wherein a top surface and a side surface of the second oxide semiconductor film are covered with the third oxide semiconductor film.

14. The semiconductor device according to claim 9, wherein a field-effect mobility of the first transistor is greater than a field-effect mobility of the third transistor.

15. The semiconductor device according to claim 9, wherein the third oxide semiconductor film, the fourth oxide semiconductor film and the fifth oxide semiconductor film are formed in a same step.

16. An electronic device comprising the semiconductor device according to claim 9.