SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

• US 20150171220A1
• Filed: 04/26/2013
• Published: 06/18/2015
• Est. Priority Date: 05/28/2012
• Status: Abandoned Application

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Tomiyasu, Kazuhide
• Application Number:
  US14/404,046
• Publication Number:
  US 20150171220A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02211 the compound being a silane, e.g. disilane, methylsilane or chlorosilane
• CPC Class Codes: H01L 21/02271 deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition H01L21/02266 takes precedence
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/02403 Oxides
• CPC Class Codes: H01L 21/477 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/38 - H01L21/449 and H01L21/461 - H01L21/475 take precedence
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

This semiconductor device (100) includes a substrate (10) and a TFT which is provided on the substrate. The TFT includes a gate electrode (12), an oxide semiconductor layer (14) which faces the gate electrode, source and drain electrodes (16, 18) which are connected to the oxide semiconductor layer, and an insulating layer (22) which contacts at least partially with the source and drain electrodes. The insulating layer (22) includes a lower region (22b) which contacts at least partially with the source and drain electrodes and an upper region (22a) which is located over the lower region. The lower region (22b) has a higher hydrogen content than the upper region (22a).

Claims

1. A semiconductor device comprising:

a substrate;

a TFT which is provided on the substrate and which includes a gate electrode, a semiconductor layer that is arranged to face the gate electrode with a gate insulating film interposed therebetween, and source and drain electrodes that are electrically connected to the semiconductor layer; and

an insulating layer formed on the source and drain electrodes,

wherein the insulating layer includes a lower region which contacts at least partially with the upper surface of the source and drain electrodes and an upper region which is located over the lower region, and

the lower region has a higher hydrogen content than the upper region.

2. The semiconductor device of claim 1, wherein the surface of at least one of the source and drain electrodes that contacts with the insulating layer is made of Cu or Mo.

3. The semiconductor device of claim 1, wherein the lower region of the insulating layer is made of SiO₂.

4. The semiconductor device of claim 1, wherein the semiconductor layer is an oxide semiconductor layer.

5. The semiconductor device of claim 4, wherein the oxide semiconductor layer is an In—

Ga—

Zn—

O based semiconductor layer.

6. The semiconductor device of claim 1, wherein the insulating layer is a passivation layer which covers the TFT.

7. The semiconductor device of claim 1, further comprising a channel protective layer which is arranged on the semiconductor layer to face the gap between the source and drain electrodes.

8. A method for fabricating a semiconductor device, the method comprising the steps of:

providing a substrate;

forming a TFT on the substrate, the TFT including a gate electrode, a semiconductor layer which is arranged to face the gate electrode with a gate insulating film interposed between them, and source and drain electrodes which are electrically connected to the semiconductor layer;

forming an insulating layer which contacts at least partially with the upper surface of the source and drain electrodes; and

conducting a heat treatment after performing the step of forming an insulating layer,

wherein the step of forming an insulating layer includes forming the insulating layer so that the content of hydrogen becomes higher in a region which is in contact with the source and drain electrodes than in a region which is out of contact with the source and drain electrodes.

9. The method of claim 8, wherein the semiconductor layer is an oxide semiconductor layer.

10. The method of claim 9, wherein the oxide semiconductor layer is an In—

Ga—

Zn—

O based semiconductor layer.

11. The method of claim 8, wherein the heat treatment is carried out at a temperature of 200°

C. to 400°

C.

12. The method of claim 8, wherein the step of forming the insulating layer includes forming an SiO₂ layer using SiH₄ gas and N₂O gas, and

in the step of forming the SiO₂ layer, an SiH₄/N₂O flow rate ratio is changed.

13. The method of claim 8, wherein the step of forming the insulating layer includes forming an SiO₂ layer by CVD process, and

in the step of forming the SiO₂ layer, an output RF voltage of the CVD process is changed.

14. The method of claim 8, wherein the step of forming the insulating layer includes forming an SiO₂ layer by CVD process, and

in the step of forming the SiO₂ layer, a film deposition pressure of the CVD process is changed.

15. The method of claim 8, wherein the step of forming the insulating layer includes forming a lower insulating layer by CVD process and forming an upper insulating layer on the lower insulating layer by sputtering process,

wherein the lower and upper insulating layers are formed so that the content of hydrogen becomes higher in the lower insulating layer than in the upper insulating layer.