IGZO TRANSISTOR STRUCTURE AND MANUFACTURING METHOD FOR THE SAME

• US 20150171225A1
• Filed: 12/17/2013
• Published: 06/18/2015
• Est. Priority Date: 12/17/2013
• Status: Active Grant

• Current Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Original Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Inventors: Tseng, Chihyuan, Shi, Longqiang
• Granted Patent: US 9,117,912 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02271 deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition H01L21/02266 takes precedence
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

The present invention provides an IGZO transistor and a manufacturing method for the same. Wherein, the method comprises forming a source electrode, a drain electrode, and an IGZO layer on a substrate; forming a protect layer at a channel of the IGZO layer; performing N-type doping to a contact region of the source/drain electrodes and the IGZO layer to form a n+IGZO region through plasma treatment; and forming a gate insulation layer and a gate electrode. The IGZO transistor structure and method for the same provided by the present invention can prevent the channel of the IGZO layer from damage during N-type doping through the plasma treatment. It can improve the ohmic contact and increase device characteristics.

Claims

1. A manufacturing method for an indium gallium zinc oxide (IGZO) transistor, comprising:

forming a source electrode, a drain electrode, and an IGZO layer on a substrate;

forming a protect layer at a channel of the IGZO layer;

performing N-type doping to a contact region of the source/drain electrodes and the IGZO layer to form a n+IGZO region through plasma treatment; and

forming a gate insulation layer and a gate electrode.

2. The manufacturing method according to claim 1, wherein, in the step of forming a protect layer at a channel of the IGZO layer, further comprises:

depositing a silicon oxide thin film on the source/drain electrodes and the IGZO layer using CVD (Chemical Vapor Deposition);

coating a photoresist on the silicon oxide thin film;

exposing and developing under a mask;

etching a region which are not protected by the photoresist; and

removing the photoresist to form the protect layer.

3. A manufacturing method for an indium gallium zinc oxide (IGZO) transistor, comprising:

forming a source electrode and a drain electrode on a substrate;

forming an IGZO layer on the source/drain electrodes and coating a photoresist;

utilizing a half-tone mask to perform exposure for the photoresist to form a protective photoresist at a channel of the IGZO layer;

performing plasma treatment at a contact region of the source/drain electrodes and the IGZO layer to form a n+IGZO region; and

forming a gate insulation layer and a gate electrode.

4. The manufacturing method according to claim 3, wherein, in the step of utilizing a half-tone mask to perform exposure for the photoresist to form a protective photoresist at a channel of the IGZO layer, further comprises:

utilizing the half-tone mask to expose a portion of the photoresist at a contact region of the source/drain electrodes and the IGZO layer, and not expose a portion of the photoresist at the channel of the IGZO; and

after utilizing wet-etching to form a pattern of IGZO layer, etching the portion of the photoresist at the contact region of the source/drain electrodes and the IGZO layer by dry etching, and the portion of the photoresist at the channel of the IGZO layer become thin to form the protective photoresist.

5. The manufacturing method according to claim 4, wherein, after forming a n+IGZO region, further comprises a step of removing the protective photoresist.

6. An indium gallium zinc oxide (IGZO) transistor structure, comprising:

a source electrode, a drain electrode, and an IGZO layer disposed on a substrate;

a protect layer covered on a channel of the IGZO layer;

n+IGZO region formed by performing N-type doping at a contact region of the source electrode, the drain electrode and the IGZO layer;

a gate insulation layer disposed on the protect layer and the n+IGZO region; and

a gate electrode disposed on the gate insulation layer.

7. The IGZO transistor structure according to claim 6, wherein, the protect layer is silicon oxide.