GATE DRIVER CIRCUIT OUTPUTTING SUPERIMPOSED PULSES

• US 20150171833A1
• Filed: 07/18/2014
• Published: 06/18/2015
• Est. Priority Date: 12/13/2013
• Status: Abandoned Application

• Current Assignee: Electronics and Telecommunications Research Institute, Konkuk University Industrial Cooperation Corp
• Original Assignee: Electronics and Telecommunications Research Institute, Konkuk University Industrial Cooperation Corp
• Inventors: PARK, Sang-Hee, RYU, Min Ki, HWANG, Chi-Sun, KWON, OhSang, PI, Jae-Eun, PARK, Eunsuk, PARK, Kee-Chan, KIM, YeonKyung
• Application Number:
  US14/335,242
• Publication Number:
  US 20150171833A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 4/026 using digital techniques
• CPC Class Codes: H03K 5/01 Shaping pulses discrimination against noise or interference H03K5/125
• CPC Class Codes: H03K 5/05 by the use of clock signals or other time reference signals

Abstract

Provided is a gate driver circuit. The gate driver circuit includes a plurality of sequentially connected stages, and each of stages includes an input unit including two input transistors forming diode connection, a pull-up unit including a pull-up transistor and a bootstrap capacitor, and first and second pull-down units each including two transistors. According to embodiments, an input capacitor is further included which is connected to a node between the input unit and the pull-up unit. In addition, a carry unit is further included which is connected to an output terminal and formed to transmit an output signal in a high state or a low state to a next stage.

Claims

1. A gate driver circuit comprising a plurality of sequentially connected stages, an Nth (where N is a natural number) stage comprising:

an input unit configured to deliver a first carry signal to a first node in response to the first carry signal delivered from an (N−

1)th stage and a first clock signal; and

a pull-up unit configured to pull-up an input signal according to a signal level at the first node and to deliver the pulled-up input signal to an output terminal,

wherein the pull-up unit comprises a bootstrap capacitor provided between the first node and the output terminal to bootstrap a signal level at the first node to a high level.

2. The gate driver circuit of claim 1, wherein the input unit comprises a first input transistor configured to deliver the first carry signal in response to the first clock signal;

and

a second input transistor configured to deliver the first carry signal to the first node in response to the first carry signal,

wherein the first input transistor is connected between a gate electrode and a drain electrode of the second transistor.

3. The gate driver circuit of claim 2, wherein the input signal input to the Nth stage is delayed than the signal input to the (N−

1)th stage, and the input signal input to the Nth stage is partially superimposed in a high level period with the input signal input to the (N−

1)th stage.

4. The gate driver circuit of claim 3, wherein a signal level at the first node is bootstrapped at a point where the first carry signal is transitioned from a high level to a low level and the input signal is transitioned from a low level to a high level.

5. The gate driver circuit of claim 4, wherein the pull-up unit comprises:

a pull-up transistor configured to deliver the input signal to an output terminal in response to the signal level at the first node.

6. The gate driver circuit of claim 5, further comprising an input capacitor connected between a gate electrode of the first input transistor and the first node to lower a voltage of the first node by capacitive coupling.

7. The gate driver circuit of claim 5, further comprising:

a first pull-down unit configured to ground the first node; and

a second pull-down unit configured to ground the output terminal.

8. The gate driver circuit of claim 7, wherein the first pull-down unit comprises:

a first pull-down transistor configured to deliver a signal at the first node in response to the first clock signal; and

a second pull-down transistor configured to ground a signal delivered from the first pull-down transistor in response to a second carry signal delivered from an (N+2)th stage.

9. The gate driver circuit of claim 8, wherein the second pull-down unit comprises:

a third pull-down transistor configured to ground the output terminal in response to the first clock signal; and

a fourth pull-down transistor configured to ground the output terminal in response to a second carry signal delivered to a second node through a coupling capacitor or the input signal delivered to the second node through the pull-down capacitor.

10. The gate driver circuit of claim 9, further comprising a transistor configured to ground the second node in response to the first clock signal.

11. The gate driver circuit of claim 9, wherein capacitive coupling of the coupling capacitor and capacitive coupling of the pull-down capacitor are cancelled.

12. The gate driver circuit of claim 10, further comprising a carry unit connected to the output terminal to deliver a signal from the output terminal to (N−

2)th and (N+1)th stages or to a power supply voltage.

13. The gate driver circuit of claim 12, wherein the carry unit comprises:

a first carry transistor configured to deliver a signal from the output terminal to a third node in response to the second clock signal; and

a second carry transistor configured to deliver a signal from the third node as the power supply voltage in response to a third clock signal,

wherein the signal of the third node is a third carry signal delivered to input units of the (N−

2)th stage and (N+1)th stage.

14. The gate driver circuit of claim 13, wherein the first to third carry signals have an identical amplitude and period, the third carry signal is delayed by ⅙

period than the first carry signal, and the second carry signal is delayed by ⅓

period than the third carry signal.

15. The gate driver circuit of claim 13, wherein the power supply voltage is lower than a ground voltage.