APPARATUS FOR REDUCING PERIODIC JITTER IN A RING OSCILLATOR

• US 20150171839A1
• Filed: 12/17/2013
• Published: 06/18/2015
• Est. Priority Date: 12/17/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Michael E. Bichan, Robert H. Wang
• Inventors: BICHAN, Michael E., WANG, Robert H.
• Granted Patent: US 9,300,277 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H03K 3/013 Modifications of generator to prevent operation by noise or interference
• CPC Class Codes: H03K 3/0315 Ring oscillators

Abstract

Described is an apparatus which comprises: a first power supply node to provide power supply current; a ring oscillator, coupled to the first power supply node, to generate an oscillating output according to change in the power supply current provided to the ring oscillator; and a second power supply node; a circuit, coupled to the second power supply node, to replicate time-average (e.g., DC) behavior of the ring oscillator; and a feedback mechanism having inputs coupled to the first and second power supply nodes, and an output to control current in the circuit.

Claims

1. An apparatus comprising:

a first power supply node to provide power supply current;

a ring oscillator, coupled to the first power supply node, to generate an oscillating output according to change in the power supply current provided to the ring oscillator; and

a second power supply node;

a circuit, coupled to the second power supply node, to replicate time-average behavior of the ring oscillator; and

a feedback mechanism having inputs coupled to the first and second power supply nodes, and an output to control current in the circuit.

2. The apparatus of claim 1, wherein the feedback mechanism comprises an operational amplifier.

3. The apparatus of claim 2, wherein the operational amplifier includes offset cancellation apparatus.

4. The apparatus of claim 1, wherein the circuit comprises:

a first p-type device coupled to the second power supply;

a second p-type device coupled in series to the first p-type device;

a first n-type device coupled in series to the second p-type device;

a second n-type device coupled to series to the first n-type device, the second n-type device controllable by the output of the feedback mechanism.

5. The apparatus of claim 4, wherein the first p-type device has a gate terminal coupled to ground.

6. The apparatus of claim 4, wherein the second p-type device has a gate terminal coupled to a drain terminal of the second n-type device.

7. The apparatus of claim 4, wherein the first n-type device has a gate terminal coupled to a drain terminal of the first p-type device.

8. The apparatus of claim 1 further comprises:

a first current source to provide current to the first and second power supply nodes; and

a first p-type pass-gate coupled to the first current source and the second power supply, the first p-type pass-gate controllable by a first signal generated by a phase detector.

9. The apparatus of claim 8 further comprises:

a second p-type pass-gate coupled to the first current source and the first power supply, the second p-type pass-gate controllable by a second signal, which is an inverse of the first signal, wherein the circuit to cause a node coupling the first current source to the first and second p-type pass-gates to have substantially constant voltage as the first signal and the second signal toggle.

10. The apparatus of claim 8 further comprises:

a second current source to provide current to the first and second power supply nodes; and

a third p-type pass-gate coupled to the second current source and the second power supply, the third p-type pass-gate controllable by a third signal generated by a phase detector.

11. The apparatus of claim 10, further comprises:

a fourth p-type pass-gate coupled to the second current source and the first power supply, the fourth p-type pass-gate controllable by a fourth signal, which is an inverse of the third signal, wherein the circuit to cause a node coupling the second current source to the third and fourth p-type pass-gates to have substantially constant voltage as the third signal and the fourth signal toggle.

12. A system comprising:

a memory unit;

a processer coupled to the memory unit, the processor including a phase locked loop including;

a first power supply node to provide power supply current;

a ring oscillator, coupled to the first power supply node, to generate an oscillating output according to change in the power supply current provided to the ring oscillator; and

a second power supply node;

a circuit, coupled to the second power supply node, to replicate time-average behavior of the ring oscillator; and

a feedback mechanism having inputs coupled to the first and second power supply nodes, and an output to control current in the circuit; and

a wireless interface for allowing the processor to communicate with another device.

13. The system of claim 12 further comprises a display unit.

14. The system of claim 12, wherein the feedback mechanism comprises an operational amplifier.

15. The system of claim 12, wherein the circuit comprises:

a first p-type device coupled to the second power supply;

a second p-type device coupled in series to the first p-type device;

a first n-type device coupled in series to the second p-type device;

a second n-type device coupled to series to the first n-type device, the second n-type device controllable by the output of the feedback mechanism.

16. The system of claim 15, wherein the first p-type device has a gate terminal coupled to ground, wherein the second p-type device has a gate terminal coupled to a drain terminal of the second n-type device, and wherein the first n-type device has a gate terminal coupled to a drain terminal of the first p-type device.

17. The system of claim 12, wherein the phase locked loop further comprises:

a current source to provide current to the first and second power supply nodes;

a first p-type pass-gate coupled to the current source and the second power supply, the first p-type pass-gate controllable by a signal generated by a phase detector; and

a second p-type pass-gate coupled to the current source and the first power supply, the second p-type pass-gate controllable by another signal, which is an inverse of the signal.

18. An apparatus comprising:

a circuit, coupled to a second power supply node, to replicate time-average behavior of a ring oscillator; and

a feedback mechanism having inputs coupled to first and second power supply nodes, and an output to control current in the circuit.

19. The apparatus of claim 18, wherein the ring oscillator is coupled to the first power supply node, the ring oscillator to generate an oscillating output according to change in power supply current provided to the ring oscillator by the first power supply node.

20. The apparatus of claim 18, wherein the feedback mechanism comprises an operational amplifier.