GATE DRIVER CIRCUIT

• US 20150171852A1
• Filed: 03/05/2014
• Published: 06/18/2015
• Est. Priority Date: 12/18/2013
• Status: Active Grant

• Current Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Original Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Inventors: PANG, Sung Man
• Granted Patent: US 9,300,285 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H03K 17/08104 in field-effect transistor switches H03K17/0812, H03K17/0814 take precedence
• CPC Class Codes: H03K 17/163 Soft switching

Abstract

A gate driver circuit may include a driving signal generating unit generating first and second control signals based on a data signal and a fault state signal and controlling gate detection, a driving inverter operating in response to the first and second control signals to generate a gate signal and providing the gate signal to a power switch element, and a soft turn-off/gate detecting unit operating in response to the second control signal, performing a soft turn-off in the case of a fault, and detecting the gate signal to provide a detected signal.

Claims

1. A gate driver circuit, comprising:

a driving signal generating unit configured to generate first and second control signals based on a data signal and a fault state signal and control gate detection;

a driving inverter configured to operate in response to the first and second control signals to generate a gate signal and provide the gate signal to a power switch element; and

a soft turn-off/gate detecting unit configured to operate in response to the second control signal, perform a soft turn-off in the case of a fault, and detect the gate signal to provide a detected signal.

2. The gate driver circuit of claim 1, wherein the driving signal generating unit generates the first control signal using the data signal and the fault state signal and generates the second control signal using the first control signal and the fault state signal.

3. The gate driver circuit of claim 1, wherein the driving signal generating unit includes:

a first inverter inverting the data signal;

a second inverter inverting the fault state signal;

an AND gate performing an AND operation on an output signal of the first inverter and an output signal of the second inverter to provide the first control signal;

a first buffer providing the first control signal to the driving inverter;

an OR gate performing an OR operation on the first control signal and the fault state signal to provide the second control signal; and

a second buffer providing the second control signal to the soft turn-off/gate detecting unit.

4. The gate driver circuit of claim 1, wherein the driving inverter includes:

a level shifter shifting a level of the second control signal;

a PMOS transistor having a source connected to an operating voltage terminal, a gate connected to an output terminal of the level shifter, and a drain; and

an NMOS transistor having a drain connected to the drain of the PMOS transistor, a gate receiving the first control signal, and a source connected to a ground,

wherein the gate signal is provided from a connection node between the PMOS transistor and the NMOS transistor via a resistor.

5. The gate driver circuit of claim 1, wherein the soft turn-off/gate detecting unit includes:

an NMOS transistor having a drain connected to a gate of the power switch element, a gate receiving the second control signal, and a source; and

a detecting resistor connected between the source of the NMOS transistor and a ground and proportionally detecting a gate voltage of the power switch element to provide the detected signal.

6. A gate driver circuit, comprising:

a driving signal generating unit configured to generate first and second control signals based on a data signal and a fault state signal and control gate detection;

a driving inverter configured to operate in response to the first and second control signals to generate a gate signal and provide the gate signal to a power switch element;

a soft turn-off/gate detecting unit configured to operate in response to the second control signal, perform a soft turn-off in the case of a fault, and detect the gate signal to provide a detected signal;

a clamp controlling unit configured to provide a gate clamp control signal based on the second control signal and the detected signal; and

an active clamp circuit unit configured to operate in response to the clamp control signal of the clamp controlling unit to connect a gate of the power switch element to a ground.

7. The gate driver circuit of claim 6, wherein the driving signal generating unit generates the first control signal using the data signal and the fault state signal and generates the second control signal using the first control signal and the fault state signal.

8. The gate driver circuit of claim 6, wherein the driving signal generating unit includes:

a first inverter inverting the data signal;

a second inverter inverting the fault state signal;

an AND gate performing an AND operation on an output signal of the first inverter and an output signal of the second inverter to provide the first control signal;

a first buffer providing the first control signal to the driving inverter;

an OR gate performing an OR operation on the first control signal and the fault state signal to provide the second control signal; and

a second buffer providing the second control signal to the soft turn-off/gate detecting unit.

9. The gate driver circuit of claim 6, wherein the driving inverter includes:

a level shifter shifting a level of the second control signal;

a PMOS transistor having a source connected to an operating voltage terminal, a gate connected to an output terminal of the level shifter, and a drain; and

an NMOS transistor having a drain connected to the drain of the PMOS transistor, a gate receiving the first control signal, and a source connected to a ground,

wherein the gate signal is provided from a connection node between the PMOS transistor and the NMOS transistor via a resistor.

10. The gate driver circuit of claim 6, wherein the soft turn-off/gate detecting unit includes:

an NMOS transistor having a drain connected to the gate of the power switch element, a gate receiving the second control signal, and a source; and

a detecting resistor connected between the source of the NMOS transistor and a ground and proportionally detecting a gate voltage of the power switch element to provide the detected signal.

11. The gate driver circuit of claim 6, wherein the clamp controlling unit includes:

an inverter inverting the detected signal;

an AND gate performing an AND operation on the second control signal and an output signal of the inverter; and

a buffer providing an output signal of the AND gate to the active clamp circuit unit as the clamp control signal.

12. The gate driver circuit of claim 6, wherein the active clamp circuit unit includes an NMOS transistor having a drain connected to the gate of the power switch element, a gate receiving the clamp control signal, and a source connected to the ground.

13. A gate driver circuit, comprising:

a driving signal generating unit configured to generate first and second control signals based on a data signal and a fault state signal and control gate detection;

a driving inverter configured to operate in response to the first and second control signals to generate a gate signal and provide the gate signal to a power switch element;

a soft turn-off/gate detecting unit configured to operate in response to the second control signal, perform a soft turn-off in the case of a fault, and detect the gate signal to provide a detected signal;

a clamp controlling unit configured to provide a gate clamp control signal based on the second control signal and the detected signal; and

an active clamp circuit unit configured to operate in response to the clamp control signal of the clamp controlling unit to connect a gate of the power switch element to a ground,

wherein the driving signal generating unit and the clamp controlling unit are implemented as a logical circuit.

14. The gate driver circuit of claim 13, wherein the driving signal generating unit generates the first control signal using the data signal and the fault state signal and generates the second control signal using the first control signal and the fault state signal.

15. The gate driver circuit of claim 13, wherein the driving signal generating unit includes:

a first inverter inverting the data signal;

a second inverter inverting the fault state signal;

an AND gate performing an AND operation on an output signal of the first inverter and an output signal of the second inverter to provide the first control signal;

a first buffer providing the first control signal to the driving inverter;

an OR gate performing an OR operation on the first control signal and the fault state signal to provide the second control signal; and

a second buffer providing the second control signal to the soft turn-off/gate detecting unit.

16. The gate driver circuit of claim 13, wherein the driving inverter includes:

a level shifter shifting a level of the second control signal;

a PMOS transistor having a source connected to an operating voltage terminal, a gate connected to an output terminal of the level shifter, and a drain; and

an NMOS transistor having a drain connected to the drain of the PMOS transistor, a gate receiving the first control signal, and a source connected to a ground,

wherein the gate signal is provided from a connection node between the PMOS transistor and the NMOS transistor via a resistor.

17. The gate driver circuit of claim 13, wherein the soft turn-off/gate detecting unit includes:

an NMOS transistor having a drain connected to the gate of the power switch element, a gate receiving the second control signal, and a source; and

a detecting resistor connected between the source of the NMOS transistor and a ground and proportionally detecting a gate voltage of the power switch element to provide the detected signal.

18. The gate driver circuit of claim 15, wherein the clamp controlling unit includes:

an inverter inverting the detected signal;

an AND gate performing an AND operation on the second control signal and an output signal of the inverter; and

a buffer providing an output signal of the AND gate to the active clamp circuit unit as the clamp control signal.

19. The gate driver circuit of claim 15, wherein the active clamp circuit unit includes an NMOS transistor having a drain connected to the gate of the power switch element, a gate receiving the clamp control signal, and a source connected to the ground.