HIGH OUTPUT POWER DIGITAL-TO-ANALOG CONVERTER SYSTEM

• US 20150171878A1
• Filed: 02/23/2015
• Published: 06/18/2015
• Est. Priority Date: 08/19/2013
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Schafferer, Bernd, ZHAO, Bing
• Granted Patent: US 10,056,924 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H03F 1/02 Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
• CPC Class Codes: H03F 1/3241 using predistortion circuits H03F1/3211, H03F1/3217 take precedence
• CPC Class Codes: H03F 3/24 of transmitter output stages
• CPC Class Codes: H03F 3/45286 Non-folded cascode stages
• CPC Class Codes: H03M 1/662 Multiplexed conversion systems
• CPC Class Codes: H03M 1/74 Simultaneous conversion
• CPC Class Codes: H03M 1/747 with equal currents which are switched by unary decoded digital signals
• CPC Class Codes: H04B 1/0475 with means for limiting noise, interference or distortion H04B1/0483 takes precedence
• CPC Class Codes: H04B 2001/045 with means for improving efficiency

Abstract

The present disclosure discloses a digital-to-analog converter (DAC) design which is suitable for providing a high output power high-speed DAC, e.g., in radio frequency applications. The DAC design utilizes a parallel DAC structure, e.g., having 8 parallel DACs and an aggregate current output, to provide a high and programmable current output (in some implementations, up to 512 mA or more). The parallel DAC structure alleviates the design problems which exist in trying to output a high amount of current using a single DAC. The DAC design further utilizes a hybrid structure which integrates the signal chain for a more reliable system. In some embodiments, the hybrid structure uses a CMOS process for the current sources and switches and a GaAs cascode stage for combining the outputs to optimally leverage the advantages of both technologies. The result is a highly efficient DAC (with peak output power programmable up to 29 dBm or more).

Claims

1. A digital to analog converter (DAC) system, the DAC comprising:

M parallel DAC cores, wherein each parallel DAC core converts a digital input signal to an analog output signal, wherein M is equal to or greater than 2; and

a cascode stage connected to the outputs of the M parallel DAC cores for combining the outputs of the M parallel DAC cores to provide an aggregate analog output.

2. The DAC system of claim 1, wherein M is equal to or greater than 4.

3. The DAC system of claim 1, wherein the cascode stage includes:

M parallel cascodes, each parallel cascode connected to a corresponding parallel DAC core; and

a power combining network to combine output power at the outputs of the cascodes.

4. The DAC system of claim 3, further comprising:

a network of traces directly connecting the outputs of the M parallel DAC cores to corresponding M parallel cascodes of the cascode stage.

5. The DAC system of claim 1, wherein:

the M parallel DAC cores and the cascode stage are fabricated using different semiconductor processes.

6. The DAC of system claim 1, wherein:

the M parallel DAC cores and the cascode stage are combined on a multi-chip module.

7. The DAC system of claim 1, wherein the M parallel DAC cores comprises M current steering DAC cores.

8. The DAC system of claim 1, further comprising:

a digital signal processor to provide input digital words arranged in a specific or random manner as the respective digital input signal of the M parallel DAC cores.

9. The DAC of claim 1, wherein:

the same input digital word is provided as the digital input signal to the M parallel DAC cores; and

the DAC system further comprises a clock signal generator to provide clock signals having different respective phases to the M parallel DAC cores.

10. The DAC system of claim 1, wherein:

the cascode stage and the M parallel DAC cores being provided on two separate dies in a multi-chip module;

the DAC system further comprises;

an operational amplifier provided on the same die as the M parallel DAC cores;

a replica current source provided on the same die as the M parallel DAC cores; and

a replica cascode provided on the same die as the cascode stage;

wherein the operational amplifier biases the replica cascode and the M parallel cascodes, and maintains drain voltages of the replica current source and current sources of the M parallel DAC cores.

11. The DAC system of claim 10, wherein the operational amplifier, the replica current source, and the replica cascode construct a feedback loop.

12. The DAC system of claim 10, wherein the positive input of the operational amplifier is connected to a reference voltage, and the negative input of the operational amplifier is connected to a drain side of the replica current source.

13. The DAC system of claim 12, wherein the reference voltage is programmable to fine tune the drain voltage of the current sources of the M parallel DAC cores.

14. The DAC system of claim 1, wherein the DAC system is part of a transmitter system, and the transmitter system further includes a digital pre-distortion processor for (1) providing an inverse of the non-linearity as input to the DAC stage and/or the cascode stage to compensate non-ideal errors of the DAC stage and/or the cascode stage and/or (2) restore the ideal waveforms to compensate the non-ideal errors present in the DAC stage and/or the cascode stage.

15. The DAC system of claim 14, wherein the digital pre-distortion processor compensates the non-ideal errors of both the DAC stage and the cascode stage using only a single set of coefficients indexed by a sample of the digital input signal.

16. The DAC system of claim 14, wherein the digital pre-distortion processor is provided in the radio-frequency (RF) domain after a modulation process of up-sampling a baseband signal into the RF domain.

17. A transmitter system for transmitting a radio frequency (RF) output, the transmitter system comprising:

M parallel DAC cores, wherein M is equal to or greater than 2, and each DAC core converts a digital input signal to an analog output signal;

a cascode stage directly connected to the outputs of the M parallel DAC cores for combining the outputs of the M parallel DAC cores to provide an aggregate analog output as the RF output; and

wherein at least a majority of the amplification or gain of the transmitter system is provided by the M parallel DAC cores and the cascode stage.

18. The transmitter system of claim 17, wherein:

a peak output power level of the transmitter system is at least 15 Decibel-milliWatts.

19. The transmitter system of claim 17, wherein the transmitter system is part of a cable modem termination system, distributed antenna system network, or micro-cell base station.

20. The transmitter system of claim 17, wherein coarse gain setting and/or fine gain adjustment is controllable through a programmable reference current of the M parallel DAC cores which directly affects the total output current of the aggregate analog output.

21. The transmitter system of claim 17, wherein:

(1) the transmitter system does not include a discrete amplification stage, OR

(2) the transmitter system further includes a discrete amplification stage, wherein the amplification or gain provided by the M parallel DAC cores and the cascode stage is greater than the gain of the discrete amplification stage.