Waveform Calibration Using Built In Self Test Mechanism
First Claim
1. A method for operating a transceiver on a chip, the method comprising:
- performing a calibration procedure comprising;
generating first constant frequency signal using an adjustable power amplifier in a transmitter portion of the transceiver at a selected operating amplitude level;
generating a second constant frequency signal having a different but similar fundamental frequency as the first constant frequency signal in a receiver portion of the transceiver;
receiving a portion of the second constant frequency signal in the receiver portion of the transceiver;
down-converting the received portion of the first constant frequency signal using the second constant frequency signal to produce low frequency harmonic components indicative of a wave-shape of the first constant frequency signal;
adjusting the power amplifier across a range of power levels while monitoring an amplitude of one or more of the low frequency harmonic components; and
selecting an operating power for the adjustable power amplifier for which the amplitude of the one or more low frequency harmonic components is below a threshold value, whereby the wave-shape of the first constant frequency signal is optimized.
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Accused Products
Abstract
A system on a chip (SoC) includes a transceiver comprising a transmitter having a power amplifier and a receiver having a signal buffer. At least one of the transmitter and receiver has a configurable portion that can be configured to produce a range of waveforms (both in waveshape as well as duty cycle). A low cost built in self test (BIST) logic is coupled to the transceiver. The BIST logic is operable to calibrate the configurable portion of the transceiver to produce a waveform that has a selected harmonic component that has an amplitude that is less than a threshold value. Current consumed by the transceiver may be dynamically reduced by selecting an optimized waveform that has low harmonic components.
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Citations
17 Claims
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1. A method for operating a transceiver on a chip, the method comprising:
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performing a calibration procedure comprising; generating first constant frequency signal using an adjustable power amplifier in a transmitter portion of the transceiver at a selected operating amplitude level; generating a second constant frequency signal having a different but similar fundamental frequency as the first constant frequency signal in a receiver portion of the transceiver; receiving a portion of the second constant frequency signal in the receiver portion of the transceiver; down-converting the received portion of the first constant frequency signal using the second constant frequency signal to produce low frequency harmonic components indicative of a wave-shape of the first constant frequency signal; adjusting the power amplifier across a range of power levels while monitoring an amplitude of one or more of the low frequency harmonic components; and selecting an operating power for the adjustable power amplifier for which the amplitude of the one or more low frequency harmonic components is below a threshold value, whereby the wave-shape of the first constant frequency signal is optimized. - View Dependent Claims (2, 3, 4)
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5. A method for operating a transceiver on a chip, the method comprising:
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placing the transceiver in a calibration mode, wherein the transceiver comprises a transmitter having a power amplifier and a receiver having a signal buffer, wherein at least one of the transmitter and receiver has a configurable portion that can be configured to produce a range of waveforms; calibrating the configurable portion of the transceiver to produce a waveform that has a selected harmonic component that has an amplitude that is less than a threshold value while operating at a selected operating amplitude by; down-converting a portion of a signal produced by the configurable portion to produce low frequency harmonic components indicative of a wave-shape of the signal; and selecting an operating power for the configurable portion for which the amplitude of the one or more low frequency harmonic components is below the threshold value. - View Dependent Claims (6, 7, 8, 9, 10)
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11. A system on a chip (SoC) comprising:
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a transceiver comprising a transmitter having a power amplifier and a receiver having a signal buffer, wherein at least one of the transmitter and receiver has a configurable portion that can be configured to produce a range of waveforms; and built in self test (BIST) logic coupled to the transceiver, wherein the BIST logic is operable to calibrate the configurable portion of the transceiver to produce a waveform that has a selected harmonic component that has an amplitude that is less than a threshold value, whereby current consumed by the transceiver is reduced. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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Specification