GRAPHICS PROCESSOR SUB-DOMAIN VOLTAGE REGULATION

• US 20150177823A1
• Filed: 12/19/2013
• Published: 06/25/2015
• Est. Priority Date: 12/19/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Maiyuran, Subramaniam, Khellah, Muhammad M., Tschanz, James W.
• Granted Patent: US 9,563,263 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Voltage regulation of processor sub-domains supplied by a same voltage domain power supply rail. Voltage to certain logic units within the voltage domain may be reduced relative to other logic units of the voltage domain, reducing idle time at high power. In an embodiment, a first voltage-regulated sub-domain includes at least one execution unit (EU) while a second voltage-regulated sub-domain includes at least one texture sampler to provide flexibility in setting the graphics core power-performance point beyond modulating active EU count through power domain (gating) control. In embodiments, a sub-domain voltage is regulated by an on-chip DLDO for fast voltage switching. Clock frequency and sub-domain voltage may be switched faster than the voltage of the voltage domain supply rail, permitting a more finely grained power management that can be responsive to EU workload demand.

Claims

1. A graphics processor core, comprising:

a first voltage domain coupled to a power supply rail operable at a domain voltage;

a first voltage sub-domain of the first voltage domain coupled to the power supply rail through a first supply branch, the first voltage sub-domain including at least one or more texture sampler; and

a second voltage sub-domain of the first voltage domain coupled to the power supply rail through a second supply branch, the second voltage sub-domain including at least one or more execution unit(EU), wherein;

at least one of the first and second supply branches is operable to convert the domain voltage down to a sub-domain voltage that maintains the sampler or EU in an active, low power state.

2. The graphics processor core of claim 1, wherein the first supply branch further comprises a voltage regulator operable to provide to the first voltage sub-domain a first sub-domain voltage that is lower than a second sub-domain voltage provided to the second voltage sub-domain.

3. The graphics processor core of claim 1, wherein the first supply branch further comprises a first voltage regulator operable to provide the first sub-domain voltage, and wherein the second supply branch further comprises a second voltage regulator operable to provide to the second voltage sub-domain a second sub-domain voltage lower than the domain voltage, and sufficient to maintain the EU in an active state.

4. The graphics processor core of claim 1, wherein:

the domain voltage is modifiable between a high voltage and a low voltage;

the first supply branch further comprises a voltage regulator operable to convert the high voltage down to the low voltage and to output the low voltage to the first sub-domain.

5. The graphics processor core of claim 1, wherein:

the domain voltage is modifiable at a first rate between a high voltage and a low voltage;

the first supply branch further comprises a voltage regulator operable to provide the first sub-domain voltage to the first voltage sub-domain; and

the voltage regulator is further operable to vary the first sub-domain voltage between the high voltage and the low voltage at a second rate that is greater than the first rate.

6. The graphics processor core of claim 1, wherein at least the second supply branch comprises a plurality of power transistors operable in a voltage regulation mode to convert the domain voltage to the reduced sub-domain voltage, and further operable in a power gating mode to deactivate at least one of the EU.

7. The graphics processor core of claim 2, further comprising:

a sub-domain voltage controller; and

wherein the voltage regulator comprises a digital low-dropout (DLDO) regulator coupled to the sub-domain voltage controller.

8. The graphics processor core of claim 2, further comprising:

a sub-domain voltage controller; and

wherein the voltage regulator comprises a digital low-dropout (DLDO) regulator coupled to the sub-domain voltage controller, the DLDO regulator further comprising;

a voltage sensor;

a switch array including a plurality of power transistors coupled in parallel across the power supply rail and an output of the DLDO; and

a digital switch controller having outputs coupled to gates of the power transistors to vary the number of transistors enabled in the switch array as a function of an output of the sub-domain voltage controller and an output of the DLDO that is coupled to the voltage sensor.

9. The graphics processor core of claim 2, further comprising:

a sub-domain voltage controller responsive to a performance parameter associated with at least one of the first and second sub-domain; and

wherein the voltage regulator comprises a digital low-dropout (DLDO) regulator coupled to the sub-domain voltage controller, the DLDO regulator further comprising;

a switch array including a plurality of power transistors coupled in parallel across the power supply rail and an output of the DLDO;

a comparator to compare an output of the sub-domain voltage controller and the output of the DLDO; and

a digital controller coupled to gates of the transistors to vary the number of transistors enabled in the switch array based on an output of the comparator.

10. The graphics processor core of claim 1, wherein:

the first voltage sub-domain includes at least the sampler, a rasterizer, and a memory interface; and

the second voltage sub-domain includes a plurality of EUs and is exclusive of the sampler, the rasterizer, and the memory interface.

11. A processing system, comprising:

a central processor core;

a graphics processor core; and

a first voltage regulator to provide power supply rails to both the central processor core and graphics processor core, wherein the graphics processor core further comprises;

a first voltage domain coupled to receive a domain voltage from one or more of the power supply rails;

a first voltage sub-domain coupled to the one or more power supply rails through a first supply branch, the first voltage sub-domain including at least a texture sampler; and

a second voltage sub-domain coupled to the one or more power supply rails through a second supply branch, the second voltage sub-domain including at least an execution unit(EU), wherein;

at least one of the first and second supply branches includes a second voltage regulator operable to reduce the domain voltage to a sub-domain voltage that maintains the sampler or EU in an active, low power state.

12. The system of claim 11, wherein the first supply branch further comprises the second voltage regulator operable to provide the first sub-domain voltage, and wherein the second supply branch further comprises a third voltage regulator operable to provide to the second voltage sub-domain a second sub-domain voltage that is lower than the domain voltage, and maintains the EU in an active state.

13. The system of claim 12, wherein:

the first voltage sub-domain includes at least the sampler, a rasterizer, and a memory interface;

the second voltage sub-domain includes a plurality of EUs and is exclusive of the sampler, rasterizer, and the memory interface;

each of the second and third voltage regulators comprises a digital low-dropout (DLDO) regulator.

14. The system of claim 12, wherein each DLDO regulator further comprises:

a voltage sensor;

a switch array including a plurality of power transistors coupled in parallel across the power supply rail and an output of the DLDO; and

a digital switch controller having outputs coupled to gates of the transistors to vary the number of transistors enabled in the switch array from zero to power gate a sub-domain to more than zero to voltage regulate a sub-domain as a function of the output of the DLDO coupled to the voltage sensor and a control signal indicative of a target sub-domain voltage.

15. A method of managing performance of a graphics processor core, the method comprising:

supplying a domain voltage over a power supply rail coupled to a voltage domain including one or more sampler and one or more execution unit (EU);

monitoring performance demand on the graphics processor core; and

regulating a first sub-domain voltage supplied from the rail and provided to the one or more sampler, based on the monitoring, to below the domain voltage independently of a second sub-domain voltage supplied from the rail and provided to the one or more EU.

16. The method of claim 15, further comprising:

operating the EU at a second sub-domain voltage that is equal to the domain voltage while operating the sampler at the first sub-domain voltage;

regulating the second sub-domain voltage to below the domain voltage; and

operating the EU at the reduced second sub-domain voltage.

17. The method of claim 16, further comprising cycling at least the second sub-domain voltage between the domain voltage and a voltage below the domain voltage to modulate the performance of the at least one EU independently from the at least one sampler.

18. The method of claim 16, further comprising increasing the domain voltage from a low voltage to a high voltage at a first rate before regulating the second sub-domain voltage down from the high voltage to the low voltage at a second rate greater than the first rate.

19. The method of claim 16, further comprising:

controlling a plurality of power transistors in a voltage regulation mode to regulate the domain voltage down to the second sub-domain voltage during a first time period; and

controlling one or more of the plurality of transistors in a power gating mode to deactivate at least one of the EU.

20. The method of claim 15, wherein regulating a first sub-domain voltage further comprises receiving a sub-domain voltage control signal;

performing a comparison of the sub-domain voltage control signal with the first sub-domain voltage; and

driving a digital controller coupled to gates of the transistors to vary, based on the comparison, a number of enabled power transistors coupled in parallel across the power supply rail and an output rail coupled to the first sub-domain.

21. At least one machine-readable storage medium including machine-readable instructions, that in response to being executed on a computing device, cause the computing device to manage performance of a graphics processor core by:

monitoring performance demand on the graphics processor core; and

based on the monitoring, regulating a first sub-domain voltage supplied to one or more sampler by a power supply rail coupled to a voltage domain including the sampler and one or more execution unit (EU) to below the domain voltage independently of a second sub-domain voltage supplied to the one or more EU.

22. The machine-readable medium of claim 21, further comprising instructions that in response to being executed on the computing device, cause the computing device to manage performance of a graphics processor core by:

operating the EU at a second sub-domain voltage that is equal to the domain voltage while operating the sampler at the first sub-domain voltage;

regulating the second sub-domain voltage to below the domain voltage; and

operating the EU at the reduced second sub-domain voltage.