METHOD OF MANAGING A MEMORY, AND A MEMORY SYSTEM

• US 20150178000A1
• Filed: 07/16/2014
• Published: 06/25/2015
• Est. Priority Date: 12/23/2013
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Jinman Han, Sangyong Yoon
• Inventors: YOON, Sangyong, HAN, Jinman
• Granted Patent: US 9,910,607 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0647 Migration mechanisms
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 29/024 in decoders

Abstract

In one embodiment, the method includes determining whether a selection transistor of a currently programmed memory string in the memory has deteriorated, and copying data in the currently programmed memory string to a different memory string of the memory if the determining determines the selection transistor has deteriorated.

Claims

1. A method of managing a memory, comprising:

determining whether a selection transistor of a currently programmed memory string in the memory has deteriorated; and

copying data in the currently programmed memory string to a different memory string of the memory if the determining determines the selection transistor has deteriorated.

2. The method of claim 1, wherein the determining comprises:

performing a verification operation on the selection transistor of the currently programmed memory string; and

determining the selection transistor has deteriorated if the verification operation fails.

3. The method of claim 2, wherein the verification operation comprises:

applying a gate voltage to a gate of the selection transistor; and

determining whether the selection transistor turns on based on output from the currently programmed memory string; and

determining that the verification operation has failed based on whether the selection transistor was determined to turn on.

4. The method of claim 2, wherein the performing applies a first gate voltage to the selection transistor, the copying applies a second gate voltage to the selection transistor, and the first gate voltage is less than the second gate voltage.

5. The method of claim 2, wherein the performing applies a gate voltage to the selection transistor, and the gate voltage is less than applied during a read operation.

8. The method of claim 1, wherein

the currently programmed memory string includes a plurality of memory cell transistors connected in series between a string selection transistor and a ground selection transistor;

and

the determining determines whether either one of the ground selection transistor and the string selection transistor has deteriorated.

9. The method of claim 1, wherein

the currently programmed memory string includes a string selection transistor, at least a first dummy memory cell transistor, a plurality of memory cell transistors, at least a second dummy memory cell transistor, and a ground selection transistor connected in series;

and

the determining determines whether either one of the ground selection transistor and the string selection transistor has deteriorated.

10. The method of claim 1, further comprising:

performing the determining in response to a command.

11. The method of claim 10, wherein the command is one of a program command and a read command.

12. The method of claim 10, wherein the command is a verification command, which indicates to perform the determining.

13. The method of claim 10, further comprising:

receiving the command from a host.

14. The method of claim 10, further comprising:

receiving the command from a memory controller associated with the memory.

15. The method of claim 10, wherein the performing performs the determining before or after an operation associated with the command.

17. The method of claim 10, wherein the performing comprises:

generating a count value indicating a number of times the command is received;

triggering performance of the determining if the count value exceeds a reference value.

18. The method of claim 17, wherein reference value is randomly generated.

19. The method of claim 17, wherein the triggering triggers performance of the determining for at least one currently programmed memory string in a memory cluster which was most recently accessed based on the command.

20. The method of claim 10, wherein the performing comprises:

generating a count value indicating a number of times the command is received for a memory cluster including the currently programmed memory string; and

triggering performance of the determining if the count value exceeds a reference value.

22. The method of claim 1, further comprising:

performing the determining based on a wear level of a memory cluster including the currently programmed memory string.

24. The method of claim 1, further comprising:

determining whether a memory cluster is had based on a number of memory strings in the memory cluster determined to be deteriorated; and

prohibiting access to the memory cluster if the memory cluster is determined to be bad.

26. The method of claim 1, wherein the memory is a vertical NAND.

6. (canceled)

7. (canceled)

16. (canceled)

21. (canceled)

23. (canceled)

25. (canceled)

27-55. -55. (canceled)