INSTRUCTIONS AND LOGIC TO PROVIDE BASE REGISTER SWAP STATUS VERIFICATION FUNCTIONALITY

• US 20150178078A1
• Filed: 12/21/2013
• Published: 06/25/2015
• Est. Priority Date: 12/21/2013
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Anvin, H. Peter, Rodgers, Scott D.
• Application Number:
  US14/138,054
• Publication Number:
  US 20150178078A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/30123 according to context, e.g. thread buffers
• CPC Class Codes: G06F 9/30189 according to execution mode, e.g. mode flag

Abstract

Instructions and logic provide base register swap status verification functionality. Embodiments include a processor having a first model specific register (MSR) to store a first base address corresponding to a segment for a first execution context and a second MSR to store a second base address corresponding to a segment for a second context. A third register stores a base register swap status field corresponding to the segment of the first and second contexts. A decode unit decodes a swap instruction and execution logic executes an exchange of the first MSR value and the second MSR value responsive to the swap instruction. The execution logic determines if said exchange of the first MSR value and the second MSR value completed successfully, and changes a value of the base register swap status field responsive to a determination that said exchange completed successfully.

Claims

1. A processor comprising:

a first model specific register (MSR) to store a first base address field corresponding to a segment for a first execution context;

a second MSR to store a second base address field corresponding to said segment for a second execution context;

a third register to store a base register swap status field corresponding to the segment of the first and second execution contexts;

a decode unit to decode a first swap instruction;

an execution unit to;

execute an exchange of the first MSR value and the second MSR value responsive to the decoded first swap instruction, determine if said exchange of the first MSR value and the second MSR value completed successfully, and change a value of the base register swap status field responsive to a determination that said exchange of the first MSR value and the second MSR value completed successfully.

2. The processor of claim 1, wherein the third register is to store a swapped FS status corresponding to an FS segment.

3. The processor of claim 1, wherein the third register is to store a swapped GS status corresponding to a GS segment.

4. The processor of claim 3, wherein said first MSR is to store a GS.base address field corresponding to the GS segment.

5. The processor of claim 4, wherein said second MSR is to store a KernelGSbase address field corresponding to the GS segment.

6. The processor of claim 1, wherein the third register is to store a swapped CS status corresponding to a CS segment attribute.

7. The processor of claim 1, further comprising said execution unit to:

determine a first state value of the base register swap status field prior to executing said exchange of the first MSR value and the second MSR value responsive to the decoded first swap instruction, and

perform a comparison of said first state value and a second state value of the base register swap status field.

8. The processor of claim 7, wherein said execution unit to:

change the value of the base register swap status field from said first state value to said second state value responsive to the determination that said exchange of the first MSR value and the second MSR value completed successfully.

9. The processor of claim 1, wherein the third register to store the base register swap status field is a portion of an MSR.

10. The processor of claim 1, wherein the third register to store the base register swap status field is a control register.

11. The processor of claim 10, wherein the third register to store the base register swap status field is an Extended Feature Enable Register (EFER).

12. The processor of claim 1, wherein the third register to store the base register swap status field is a flags register.

13. The processor of claim 12, wherein the third register to store the base register swap status field is a 32-bit extended flags (EFLAGS) register.

14. The processor of claim 12, wherein the third register to store the base register swap status field is a 64-bit rex-extended flags (RFLAGS) register.

15. A method comprising:

decoding a swap GS instruction;

executing an exchange of a GS base register value and a kernel GS base register value responsive to the decoded swap GS instruction;

determining if said exchange of the GS base register value and the kernel GS base register value completed successfully; and

inverting a swapped GS status responsive to a determination that said exchange of the GS base register value and the kernel GS base register value completed successfully.

16. The method of claim 15 further comprising:

performing a read of the swapped GS status from a model specific register (MSR).

17. The method of claim 16 wherein said performing the read of the swapped GS status from the MSR is to determine a second state value of the swapped GS status after executing said exchange of the GS base register value and the kernel GS base register value responsive to the decoded swap GS instruction.

18. The method of claim 17 further comprising:

determining a first state value of the swapped GS status prior to executing said exchange of the GS base register value and the kernel GS base register value responsive to the decoded swap GS instruction; and

performing a comparison of said first state value and said second state value of the swapped GS status.

19. The method of claim 18 wherein said determining the first state value of the swapped GS status prior to executing said exchange of the GS base register value and the kernel GS base register value responsive to the decoded swap GS instruction, is accomplished by performing a prior read of the swapped GS status from the MSR, prior to executing said exchange of the GS base register value and the kernel GS base register value responsive to the decoded swap GS instruction.

20. The method of claim 18 wherein said determining the first state value of the swapped GS status prior to executing said exchange of the GS base register value and the kernel GS base register value responsive to the decoded swap GS instruction, is accomplished by performing a prior write of the swapped GS status to the MSR, prior to executing said exchange of the GS base register value and the kernel GS base register value responsive to the decoded swap GS instruction.

21. The method of claim 16 wherein said performing the read of the swapped GS status from the MSR is to return said swapped GS status as a field in the register pair EDX:

EAX from the MSR specified by a value in the register ECX.

22. The method of claim 16 wherein said performing the read of the swapped GS status from the machine specific register (MSR) is to determine a first state value of the swapped GS status prior to executing said exchange of the GS base register value and the kernel GS base register value.

23. The method for claim 15 wherein said swap GS instruction includes at least an opcode having a hexadecimal value of 0F, 01, and an addressing form field comprised of a ModR/M byte having a hexadecimal value of F8.

24. The method for claim 15 wherein said determining if said exchange of the GS base register value and the kernel GS base register value completed successfully is also performed responsive to the decoded swap GS instruction.

25. The method for claim 24 wherein said inverting the swapped GS status responsive to said determination is also performed responsive to the decoded swap GS instruction.

26. A machine-readable medium to record functional descriptive material including a first executable instruction, which if executed by a machine causes the machine to:

exchange a segment base register value and a kernel segment base register value responsive to the first executable instruction;

determining if said exchange of the segment base register value and the kernel segment base register value completed successfully; and

change a base register swapped status value responsive to a determination that said exchange of the segment base register value and the kernel segment base register value completed successfully.

27. The machine-readable medium of claim 26, wherein the segment base register value corresponds to an FS segment.

28. The machine-readable medium of claim 26, wherein the segment base register value corresponds to an GS segment.

29. The machine-readable medium of claim 28, wherein said segment base register value corresponds to a GS.base address field in a first model specific register (MSR).

30. The machine-readable medium of claim 29, wherein said kernel segment base register value corresponds to a KernelGSbase address field in a second MSR.

31. The machine-readable medium of claim 30, wherein said first executable instruction is a SwapGS instruction that includes at least an opcode having a hexadecimal value of 0F, 01, and an addressing form field comprised of a ModR/M byte having a hexadecimal value of F8.

32. The machine-readable medium of claim 26, wherein said change of the base register swapped status value comprises a one-bit logical inversion.

33. The machine-readable medium of claim 32, wherein the base register swap status field is stored in a 64-bit rex-extended flags (RFLAGS) register.

34. The machine-readable medium of claim 32, wherein the base register swap status field is stored in an Extended Feature Enable Register (EFER).

35. The machine-readable medium of claim 32, wherein the base register swap status field is stored in an MSR.

36. The machine-readable medium of claim 32, wherein the base register swap status field is stored in a control register.

37. A processing system comprising:

a system memory to store an executable system page including a first instruction; and

a processor comprising;

a first model specific register (MSR) to store a first base address field corresponding to a segment for a first execution context;

a second MSR to store a second base address field corresponding to said segment for a second execution context;

a third register to store a base register swap status field corresponding to the segment of the first and second execution contexts;

a decode unit to decode the first instruction;

an execution unit to;

execute an exchange of the first MSR value and the second MSR value responsive to the decoded first instruction, determine if said exchange of the first MSR value and the second MSR value completed successfully, and change a value of the base register swap status field responsive to a determination that said exchange of the first MSR value and the second MSR value completed successfully.

38. The processing system of claim 37, wherein the segment base register value corresponds to an FS segment.

39. The processing system of claim 37, wherein the segment base register value corresponds to an GS segment.

40. The processing system of claim 39, wherein said first instruction is a SwapGS instruction that includes at least an opcode having a hexadecimal value of 0F, 01, and an addressing form field comprised of a ModR/M byte having a hexadecimal value of F8.

41. The processing system of claim 37, wherein the third register to store the base register swap status field is a flags register.

42. The processing system of claim 37, wherein the third register to store the base register swap status field is a control register.

43. The processing system of claim 37, wherein the third register to store the base register swap status field is an MSR.

44. A method comprising:

decoding a swap FS instruction;

executing an exchange of a FS base register value and a kernel FS base register value responsive to the decoded swap FS instruction;

determining if said exchange of the FS base register value and the kernel FS base register value completed successfully; and

inverting a swapped FS status responsive to a determination that said exchange of the FS base register value and the kernel FS base register value completed successfully.

45. The method of claim 44 further comprising:

performing a read of the swapped FS status from a model specific register (MSR).