LOAD SYNCHRONIZATION WITH STREAMING THREAD COHORTS

• US 20150178089A1
• Filed: 12/23/2013
• Published: 06/25/2015
• Est. Priority Date: 12/23/2013
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Brunheroto, Jose R., Cher, Chen-Yong, Franke, Hubertus, Naghmouchi, Jamin
• Granted Patent: US 9,417,882 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/383 Operand prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3887 controlled by a single instruction for multiple data lanes [SIMD]
• CPC Class Codes: G06F 9/3888 controlled by a single instruction for multiple threads [SIMT] in parallel

Abstract

There is provided a processor implemented method for controlling a lock-stepped cohort. The method includes receiving instructions for each of a first lane and a second lane. The first lane is for the lock-stepped cohort and the second lane is for another cohort. The method further includes detecting a condition in which a first instruction at the first lane will have a higher latency than a second instruction at the second lane. The method also includes setting an indicator indicating where the first lane encountered the first instruction. The method additionally includes setting the first lane to inactive, while keeping the second lane active. The method further includes setting the first lane to active on a subsequent opportunity to execute said first instruction.

Claims

1. A processor implemented method for controlling a lock-stepped cohort, the method comprising:

receiving instructions for each of a first lane and a second lane, the first lane for the lock-stepped cohort and the second lane for another cohort;

detecting a condition in which a first instruction at the first lane will have a higher latency than a second instruction at the second lane;

setting an indicator indicating where the first lane encountered the first instruction;

setting the first lane to inactive, while keeping the second lane active; and

setting the first lane to active on a subsequent opportunity to execute said first instruction.

2. The method of claim 1, wherein the other cohort needs to load data on demand.

3. The method of claim 1, wherein the first lane and the second lane are any of threads and Single Instruction Multiple Data slots.

4. The method of claim 1, wherein said step of setting the first lane to inactive comprises setting a shared flag, the shared flag for indicating, when set, that the lock-stepped cohort needs to issue a load for a next buffer.

5. The method of claim 4, wherein said step of setting the first lane to active comprises resetting the shared flag when the load is completed, the shared flag for indicating, when reset, that the next buffer is available.

6. The method of claim 1, further comprising issuing a no operation or other operation by the other cohort in lock step with the lock-stepped cohort when the lock-stepped cohort issues a load.

7. A non-transitory article of manufacture tangibly embodying a computer readable program which when executed causes a computer to perform the steps of claim 1.

8. An apparatus for controlling a lock-stepped cohort, the apparatus comprising:

a processor for receiving instructions for each of a first lane and a second lane, for detecting a condition in which a first instruction at the first lane will have a higher latency than a second instruction at the second lane, for setting an indicator indicating where the first lane encountered the first instruction, for setting the first lane to inactive, while keeping the second lane active, and for setting said first lane to active on a subsequent opportunity to execute said first instruction,

wherein the first lane is for the lock-stepped cohort and the second lane is for another cohort.

9. The apparatus of claim 8, wherein the other cohort needs to load data on demand.

10. The apparatus of claim 8, wherein the first lane and the second lane are any of threads and Single Instruction Multiple Data slots.

11. The apparatus of claim 8, wherein the first lane is set to inactive by setting a shared flag, the shared flag for indicating, when set, that the lock-stepped cohort needs to issue a load for a next buffer.

12. The apparatus of claim 11, wherein the first lane is set to active by resetting the shared flag when the load is completed, the shared flag for indicating, when reset, that the next buffer is available.

13. A processor implemented method for improving performance through data pre-loading for first and second lock-stepped cohort members of which only the first member needs to loads data on demand and the second member pre-loads data in lock-step with the first member, the method comprising:

setting a shared flag if any of the members need to issue a demand-load for a next buffer;

issuing the demand-load by both of the members, when the shared flag is set by both of the members;

examining whether a buffer and the data of the second member are ready for a pre-load, when the shared flag is set by only the first member;

reading the data by the second member in lock step with the first member, when the shared flag is set and the pre-load is deemed possible;

issuing no operation by the second member and issuing the demand-load by the first member, when the shared flag is set and the pre-load is deemed not possible;

resetting the shared flag, when the demand-load is completed; and

setting a status bit to indicate the buffer for the second member has been pre-loaded, when the pre-load is complete.

14. The method of claim 13, further comprising using the shared flag, by any of the members, to notify other ones of the members that a notifying one of the members needs to load data.

15. The method of claim 13, further comprising issuing a no operation or other operation by the second member in lock step with the first member, when the first member issues the demand-load.

16. The method of claim 13, further comprising determining if the buffer and the data of the second member are ready for pre-loading before the data of the second member is needed.

17. The method of claim 13, further comprising one of setting, reading, or resetting a status of the buffer of the second member to one of indicate or determine whether the buffer is available for a pre-load still being used, or pre-loaded, respectively.

18. The method of claim 13, further comprising allocating an available buffer for pre-loading if multiple buffers exist and are accessible by the second member.

19. The method of claim 13, further comprising setting a status, in a register or in a local memory, to indicate that the buffer of the second member is ready for pre-loading.

20. A non-transitory article of manufacture tangibly embodying a computer readable program which when executed causes a computer to perform the steps of claim 13.