HIERARCHICAL AND PARALLEL PARTITION NETWORKS

• US 20150178092A1
• Filed: 12/20/2013
• Published: 06/25/2015
• Est. Priority Date: 12/20/2013
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Asit K. Mishra, David S. Dunning, Howard S. David
• Inventors: DUNNING, David S., MISHRA, Asit K., DAVID, Howard S.
• Application Number:
  US14/137,108
• Publication Number:
  US 20150178092A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 15/163 Interprocessor communication
• CPC Class Codes: G06F 15/17362 hierarchical topologies

Abstract

In accordance with the present description, provided are hierarchical and parallel partition networks which include a plurality of parallel partition packet networks for interconnecting components on one or more integrated circuit dies. In one embodiment, each parallel partition packet network is independent of the other parallel partition packet networks and has a unit level switch at a unit hierarchical level. In another aspect, each parallel partition packet network has a unit-to-unit level switch at a unit-to-unit hierarchical level. Other aspects are described herein.

Claims

1. A system, comprising:

a memory;

a plurality of blocks defining a block hierarchical level, each block including a plurality of processors and a block network interconnecting the processors of the block;

a unit defining a unit hierarchical level higher than the block hierarchical level, said unit including a plurality of said blocks at the block hierarchical level; and

a plurality of parallel partition packet networks, each parallel partition packet network being independent of the other parallel partition packet networks of the plurality of parallel partition packet networks, each parallel partition packet network having a unit level switch at the unit hierarchical level coupled to the memory and to each block network of the plurality of blocks of the unit.

2. The system of claim 1 further comprising parallel partition packet network control logic adapted to select a first parallel partition packet network of the plurality of parallel partition packet networks, and transmit a packet through the selected parallel partition packet network independent of the other parallel partition packet networks, said transmitting including switching the packet through the unit level switch of the selected parallel partition packet network at the unit hierarchical level.

3. The system of claim 2 further comprising a plurality of said units defining a unit-to-unit hierarchical level higher than the unit hierarchical level, wherein each unit is at the unit hierarchical level and comprises a plurality of said blocks at the block hierarchical level, wherein each parallel partition packet network has a unit level switch at the unit hierarchical level for each unit and coupled to the memory and to each block network of the plurality of blocks of the particular unit, and a unit-to-unit level switch at the unit-to-unit hierarchical level and coupled to each unit level switch of the particular parallel partition packet network at the unit hierarchical level, wherein the parallel partition packet network control logic is further adapted to switch the packet through the unit-to unit level switch of the selected parallel partition packet network at the unit-to-unit hierarchical level, between selected unit level switches of the selected parallel partition packet network.

4. The system of claim 2 further comprising a first die, a second die and a plurality of die-to-die communication channels, each parallel partition packet network having a die-to-die communication channel of the plurality of die-to-die communication channels, coupled to the first and second dies, wherein the unit of the plurality of blocks and the unit level switches of the plurality of parallel partition packet networks are on the first die, the device further comprising a plurality of buffers on the first die, each parallel partition packet network having a buffer coupled to the unit level switch and the die-to-die communication channel of the particular parallel partition packet network, wherein the parallel partition packet network control logic is further adapted to buffer a packet in the buffer of the selected parallel partition packet network before transmitting the packet to the die-to-die communication channel of the selected parallel partition packet network, and to buffer a packet in the buffer received from the die-to-die communication channel of the selected parallel partition packet network in the buffer of the selected parallel partition packet network.

5. The system of claim 4 further comprising a plurality of unit hierarchical level memory controllers on the second die, each unit level memory controller adapted to control memory transactions between the memory and the processors of an associated unit, a plurality of unit level switches on the second die, wherein each parallel partition packet network has a unit level switch of the plurality of unit level switches on the second die, and a buffer of the plurality of buffers on the second die, each unit level switch on the second die coupled to the unit level switch and buffer of the particular parallel partition packet network on the first die.

6. The system of claim 5 wherein each memory controller has parallel partition packet network control logic on the second die adapted to switch a packet through the unit level switch of the selected parallel partition packet network on the second die, to buffer a packet in the buffer of the selected parallel partition packet network one the second die before transmitting the packet to the die-to-die communication channel of the selected parallel partition packet network, and to buffer a packet in the buffer on the second die received from the die-to-die communication channel of the selected parallel partition packet network on the second die.

7. The system of claim 2 further comprising a common communication channel for carrying packets from each of the plurality of parallel partition packet networks wherein each packet carried by the common communication channel has a tag identifying a parallel partition packet network, and a common unit level switch coupled to each parallel partition packet network of the plurality of parallel partition packet networks, wherein the parallel partition packet network control logic is adapted to tag a packet from each parallel partition packet network with a tag to identify the parallel partition packet network from which the packet arrived, and switch the tagged packet through the common unit level switch to the common communication channel.

8. The system of claim 7 wherein the parallel partition packet network control logic is adapted read a tag of a packet from the common communication channel, and to switch the packet through the common unit level switch to the parallel partition packet network identified by the tag of the packet.

9. A method, comprising:

parallel partition packet network control logic selecting a first parallel partition packet network of a plurality of parallel partition packet networks, coupling a memory of a device, to a plurality of blocks defining a block hierarchical level, each block including a plurality of processors and a block network interconnecting the processors of the block, wherein a plurality of said blocks is organized in at least one unit defining a unit hierarchical level higher than the first hierarchical level, each parallel partition packet network having a unit level switch at the unit hierarchical level coupled to the memory and to each block network of the plurality of blocks of the unit; and

parallel partition packet network control logic transmitting a packet through the selected parallel partition packet network independent of the other parallel partition packet networks, said transmitting including switching the packet through a unit level switch of the selected parallel partition packet network at the unit hierarchical level.

10. The method of claim 9 further comprising

parallel partition packet network control logic switching the packet through a unit-to unit level switch of the selected parallel partition packet network at a unit-to-unit hierarchical level, between selected unit level switches of the selected parallel partition packet network,

wherein a plurality of said units define the unit-to-unit level of a third hierarchical level higher than the second hierarchical level, wherein each unit is at the unit hierarchical level and comprises a plurality of said blocks at the block hierarchical level, wherein each parallel partition packet network has a unit level switch at the unit hierarchical level for each unit and coupled to the memory and to each block network of the plurality of blocks of the particular unit, and a unit-to-unit level switch at the unit-to-unit hierarchical level and coupled to each unit level switch of the particular parallel partition packet network at the unit hierarchical level.

11. The method of claim 10 further comprising parallel partition packet network control logic buffering on a first die, a packet in a buffer of the selected parallel partition packet network, each parallel partition packet network having a buffer and a die-to-die communication channel at the unit hierarchical level, each buffer of a parallel partition packet network being coupled to the die-to-die communication channel and the unit level switch of the particular parallel partition packet network, the method further comprising parallel partition packet network control logic transmitting a packet from a buffer to a die-to-die communication channel of the selected parallel partition packet network, receiving a packet from the die-to-die communication channel of the selected parallel partition packet network, and buffering the received packet in the buffer of the selected parallel partition packet network.

12. The method of claim 11 further comprising a unit level memory controller of a plurality of unit hierarchical level memory controllers on a second die, controlling memory transactions between a memory and the processors of an associated unit, each unit having an associated memory controller of the plurality of unit level memory controllers on the second die;

parallel partition packet network control logic on the second die switching a packet received from the die-to-die communication channel of the selected parallel partition packet network, through a unit level switch of the selected parallel partition packet network on the second die, each parallel partition packet network having a unit level switch of a plurality of unit level switches on the second die; and

parallel partition packet network control logic buffering on a second die, a packet received from the die-to-die communication channel of the selected parallel partition packet network in a buffer of the selected parallel partition packet network, each parallel partition packet network having a buffer of a plurality of buffers on the second die, coupled to the unit level switch of the particular parallel partition packet network, each unit level switch on the second die being coupled to the die-to-die communication channel of the particular parallel partition packet network.

13. The method of claim 12 further comprising parallel partition packet network control logic on the second die switching a packet through a unit level switch of the selected parallel partition packet network on the second die, buffering a packet in the buffer of the selected parallel partition packet network on the second die, and transmitting a packet from the buffer of the selected parallel partition packet network to the die-to-die communication channel of the selected parallel partition packet network.

14. The method of claim 13 further comprising parallel partition packet network control logic tagging a packet arriving from the selected parallel partition packet network with a tag to identify the selected parallel partition packet network from which the packet arrived, and switching the tagged packet through a common unit level switch to a common communication channel coupled to each parallel partition packet network of the plurality of parallel partition packet networks, for carrying packets from each of the plurality of parallel partition packet networks wherein each packet carried by the common communication channel has a tag identifying a parallel partition packet network from which the tagged packet arrived.

15. The method of claim 14 further comprising parallel partition packet network control logic reading a tag of a packet arrived from the common communication channel, and switching the arrived packet through the common unit level switch to the parallel partition packet network identified by the tag of the packet.

16. A device for use with a memory, comprising:

a plurality of blocks defining a block hierarchical level, each block including a plurality of processors and a block network interconnecting the processors of the block;

a unit defining a unit hierarchical level higher than the block hierarchical level, said unit including a plurality of said blocks at the block hierarchical level; and

a plurality of parallel partition packet networks, each parallel partition packet network being independent of the other parallel partition packet networks of the plurality of parallel partition packet networks, each parallel partition packet network having a unit level switch at the unit hierarchical level coupled to the memory and to each block network of the plurality of blocks of the unit.

17. The device of claim 16 further comprising parallel partition packet network control logic adapted to select a first parallel partition packet network of the plurality of parallel partition packet networks, and transmit a packet through the selected parallel partition packet network independent of the other parallel partition packet networks, said transmitting including switching the packet through the unit level switch of the selected parallel partition packet network at the unit hierarchical level.

18. The device of claim 17 further comprising a plurality of said units defining a unit-to-unit hierarchical level higher than the unit hierarchical level, wherein each unit is at the unit hierarchical level and comprises a plurality of said blocks at the block hierarchical level, wherein each parallel partition packet network has a unit level switch at the unit hierarchical level for each unit and coupled to the memory and to each block network of the plurality of blocks of the particular unit, and a unit-to-unit level switch at the unit-to-unit hierarchical level and coupled to each unit level switch of the particular parallel partition packet network at the unit hierarchical level, wherein the parallel partition packet network control logic is further adapted to switch the packet through the unit-to unit level switch of the selected parallel partition packet network at the unit-to-unit hierarchical level, between selected unit level switches of the selected parallel partition packet network.

19. The device of claim 17 further comprising a first die, a second die and a plurality of die-to-die communication channels, each parallel partition packet network having a die-to-die communication channel of the plurality of die-to-die communication channels, coupled to the first and second dies, wherein the unit of the plurality of blocks and the unit level switches of the plurality of parallel partition packet networks are on the first die, the device further comprising a plurality of buffers on the first die, each parallel partition packet network having a buffer coupled to the unit level switch and the die-to-die communication channel of the particular parallel partition packet network, wherein the parallel partition packet network control logic is further adapted to buffer a packet in the buffer of the selected parallel partition packet network before transmitting the packet to the die-to-die communication channel of the selected parallel partition packet network, and to buffer a packet in the buffer received from the die-to-die communication channel of the selected parallel partition packet network in the buffer of the selected parallel partition packet network.

20. The device of claim 19 further comprising a plurality of unit hierarchical level memory controllers on the second die, each unit level memory controller adapted to control memory transactions between the memory and the processors of an associated unit, a plurality of unit level switches on the second die, wherein each parallel partition packet network has a unit level switch of the plurality of unit level switches on the second die, and a buffer of the plurality of buffers on the second die, each unit level switch on the second die coupled to the unit level switch and buffer of the particular parallel partition packet network on the first die.

21. The device of claim 20 wherein each memory controller has parallel partition packet network control logic on the second die adapted to switch a packet through the unit level switch of the selected parallel partition packet network on the second die, to buffer a packet in the buffer of the selected parallel partition packet network one the second die before transmitting the packet to the die-to-die communication channel of the selected parallel partition packet network, and to buffer a packet in the buffer on the second die received from the die-to-die communication channel of the selected parallel partition packet network on the second die.

22. The device of claim 17 further comprising a common communication channel for carrying packets from each of the plurality of parallel partition packet networks wherein each packet carried by the common communication channel has a tag identifying a parallel partition packet network, and a common unit level switch coupled to each parallel partition packet network of the plurality of parallel partition packet networks, wherein the parallel partition packet network control logic is adapted to tag a packet from each parallel partition packet network with a tag to identify the parallel partition packet network from which the packet arrived, and switch the tagged packet through the common unit level switch to the common communication channel.

23. The device of claim 22 wherein the parallel partition packet network control logic is adapted read a tag of a packet from the common communication channel, and to switch the packet through the common unit level switch to the parallel partition packet network identified by the tag of the packet.