HIERARCHICAL AND PARALLEL PARTITION NETWORKS
First Claim
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1. A system, comprising:
- a memory;
a plurality of blocks defining a block hierarchical level, each block including a plurality of processors and a block network interconnecting the processors of the block;
a unit defining a unit hierarchical level higher than the block hierarchical level, said unit including a plurality of said blocks at the block hierarchical level; and
a plurality of parallel partition packet networks, each parallel partition packet network being independent of the other parallel partition packet networks of the plurality of parallel partition packet networks, each parallel partition packet network having a unit level switch at the unit hierarchical level coupled to the memory and to each block network of the plurality of blocks of the unit.
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Abstract
In accordance with the present description, provided are hierarchical and parallel partition networks which include a plurality of parallel partition packet networks for interconnecting components on one or more integrated circuit dies. In one embodiment, each parallel partition packet network is independent of the other parallel partition packet networks and has a unit level switch at a unit hierarchical level. In another aspect, each parallel partition packet network has a unit-to-unit level switch at a unit-to-unit hierarchical level. Other aspects are described herein.
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Citations
23 Claims
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1. A system, comprising:
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a memory; a plurality of blocks defining a block hierarchical level, each block including a plurality of processors and a block network interconnecting the processors of the block; a unit defining a unit hierarchical level higher than the block hierarchical level, said unit including a plurality of said blocks at the block hierarchical level; and a plurality of parallel partition packet networks, each parallel partition packet network being independent of the other parallel partition packet networks of the plurality of parallel partition packet networks, each parallel partition packet network having a unit level switch at the unit hierarchical level coupled to the memory and to each block network of the plurality of blocks of the unit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method, comprising:
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parallel partition packet network control logic selecting a first parallel partition packet network of a plurality of parallel partition packet networks, coupling a memory of a device, to a plurality of blocks defining a block hierarchical level, each block including a plurality of processors and a block network interconnecting the processors of the block, wherein a plurality of said blocks is organized in at least one unit defining a unit hierarchical level higher than the first hierarchical level, each parallel partition packet network having a unit level switch at the unit hierarchical level coupled to the memory and to each block network of the plurality of blocks of the unit; and parallel partition packet network control logic transmitting a packet through the selected parallel partition packet network independent of the other parallel partition packet networks, said transmitting including switching the packet through a unit level switch of the selected parallel partition packet network at the unit hierarchical level. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. A device for use with a memory, comprising:
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a plurality of blocks defining a block hierarchical level, each block including a plurality of processors and a block network interconnecting the processors of the block; a unit defining a unit hierarchical level higher than the block hierarchical level, said unit including a plurality of said blocks at the block hierarchical level; and a plurality of parallel partition packet networks, each parallel partition packet network being independent of the other parallel partition packet networks of the plurality of parallel partition packet networks, each parallel partition packet network having a unit level switch at the unit hierarchical level coupled to the memory and to each block network of the plurality of blocks of the unit. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23)
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Specification