METHOD TO DISTRIBUTE USER DATA AND ERROR CORRECTION DATA OVER DIFFERENT PAGE TYPES BY LEVERAGING ERROR RATE VARIATIONS

• US 20150178149A1
• Filed: 02/05/2014
• Published: 06/25/2015
• Est. Priority Date: 12/20/2013
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Cai, Yu, Chen, Ning, Wu, Yunxiang, Haratsch, Erich F., Cohen, Earl T., Canepa, Timothy L.
• Granted Patent: US 9,262,268 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD

Abstract

An apparatus includes a memory and a controller. The memory includes a plurality of memory devices. Each memory device has a plurality of page types. The plurality of page types are classified based on error rate variations. The controller may be configured to write user data and error-correction data to the memory. The user data and the error-correction data are organized as a super-page. The super-page includes a plurality of sub-pages. The plurality of sub-pages are written across the plurality of memory devices such that the plurality of sub-pages are stored using more than one of the plurality of page types.

Claims

1. An apparatus comprising:

a memory comprising a plurality of memory devices, each memory device having a plurality of page types, wherein said plurality of page types are classified based on error rate variations; and

a controller configured to write user data and error-correction data to said memory, wherein said user data and said error-correction data is organized as a super-page, said super-page comprises a plurality of sub-pages, and said plurality of sub-pages are written across said plurality of memory devices such that said plurality of sub-pages are stored using more than one of said plurality of page types.

2. The apparatus according to claim 1, wherein said plurality of page types comprise one or more of upper and lower pages, odd and even pages, and least significant bit and most significant bit pages.

3. The apparatus according to claim 1, wherein adjacent sub-pages are stored in different page types.

4. The apparatus according to claim 1, wherein said plurality of page types are based one or more of physical location within each of said memory devices and logical location in a memory cell.

5. The apparatus according to claim 1, wherein said controller stores said user data across said plurality of memory devices using a barber pole pattern.

6. The apparatus according to claim 1, wherein said plurality of memory devices comprise one or more flash memory dies.

7. The apparatus according to claim 1, wherein said memory and said controller are part of a solid state drive or disk.

8. The apparatus according to claim 1, wherein said controller calculates parity data in a number of steps corresponding to a number of page types used to store user data.

9. The apparatus according to claim 1, wherein said controller writes each row of user data to memory immediately and writes parity data for a plurality of rows simultaneously.

10. A method of distributing data over a plurality of memory devices comprising the steps of:

classifying each of a plurality of pages of a plurality of memory devices as one of a plurality of page types, wherein said plurality of page types are classified based on error rate variations; and

writing user data and error-correction data to said plurality of memory devices, wherein said user data and said error-correction data is organized as a super-page, said super-page comprises a plurality of sub-pages, and said plurality of sub-pages are written across said plurality of memory devices such that said plurality of sub-pages are stored using more than one of said plurality of page types.

11. The method according to claim 10, wherein said plurality of page types comprise one or more of upper and lower pages, odd and even pages, and least significant bit and most significant bit pages.

12. The method according to claim 10, wherein adjacent sub-pages are stored in different page types.

13. The method according to claim 10, wherein said plurality of page types are based one or more of physical location within each of said memory devices and logical location in a memory cell.

14. The method according to claim 10, wherein said user data is stored across said plurality of memory devices using a barber pole pattern.

15. The method according to claim 10, further comprising calculating parity data in a number of steps corresponding to a number of page types used to store user data.

16. The method according to claim 10, further comprising writing each row of user data to memory immediately and writing parity data for a plurality of rows simultaneously.