MEMORY SYSTEM

• US 20150178156A1
• Filed: 05/21/2014
• Published: 06/25/2015
• Est. Priority Date: 12/24/2013
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: SHIN, Beom Ju
• Granted Patent: US 9,442,797 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 11/1612 where the redundant component is persistent storage
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 2029/5004 Voltage
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators

Abstract

A memory system is provided. The memory system includes a memory device suitable for reading out data from memory cells by a plurality of read voltages having various levels, and a controller suitable for updating probabilistic information based on the read out data when the read out data is input to the controller, and performing an error correction operation by the updated probabilistic information, wherein the controller updates the probabilistic information a predetermined number of times that the memory device reads out the data.

Claims

1. A memory system comprising:

a memory device suitable for reading out data from memory cells by a plurality of read voltages having various levels; and

a controller suitable for updating probabilistic information based on the read out data when the read out data is input to the controller, and performing an error correction operation by the updated probabilistic information,

wherein the controller updates the probabilistic information predetermined number of times that the memory device reads out the data.

3. The memory system of claim 1, wherein the controller further comprises a buffer suitable for storing the read out data.

4. The memory system of claim 3, wherein the controller replaces a previously read out data stored in the buffer with a currently read out data.

5. The memory system of claim 1, wherein the controller comprises:

a probabilistic information generator suitable for updating the probabilistic information based on the read out data when the memory device reads out the data and provides the read out data to the controller, and

an error correction block suitable for performing the error correction operation by the probabilistic information updated by the probabilistic information generator.

6. The memory system of claim 5, wherein the probabilistic information generator comprises:

a sampling counter suitable for generating a count value representing a number of times that the memory device provides the read out data to the controller;

a probabilistic information lookup table suitable for providing information for updating the probabilistic information in response to the count value;

a buffer suitable for storing the read out data; and

a probabilistic information register suitable for updating the probabilistic information based on the read out data stored in the buffer and the information provided from the probabilistic information lookup table.

7. The memory system of claim 6, wherein an amount of the information provided from the probabilistic information lookup table varies depending on the predetermined number of times.

8. The memory system of claim 6, wherein the probabilistic information generator replaces a previously read out data stored in the buffer with a currently read out data.

9. The memory system of claim 1, wherein the memory device sequentially uses the read voltages in ascending order of voltage levels to read the data from the memory cells.

10. The memory system of claim 1, wherein the memory device sequentially uses the read voltages in descending order of voltage levels to read the data from the memory cells.

11. The memory system of claim 1, wherein the memory device reads data from the memory cells by use of the various levels of read voltages to distinguish a first threshold voltage distribution and a second threshold voltage distribution that are adjacent to each other.

2. The memory system of claim wherein the controller updates the probabilistic information while the memory device reads out the data from the memory cells.

15. The memory system of claim 2, wherein the probabilistic information generator comprises:

a sampling counter suitable for generating a count value representing a number of times that the read out data is stored in the storage unit;

a probabilistic information lookup table suitable for providing information for updating the probabilistic information in response to the count value; and

a probabilistic information register suitable for updating the probabilistic information based on the read out data stored in the storage unit and the information provided from the probabilistic information lookup table.

16. The memory system of claim 15, wherein an amount of the information provided from the probabilistic information lookup table varies depending on the predetermined number of times.

12. A memory system comprising:

a storage unit suitable for storing read out data read from a memory device;

a probabilistic information generator suitable for updating probabilistic information based on the read out data when the read out data is stored in the storage unit; and

an error correction block suitable for performing an error correction operation on data by the updated probabilistic information,

wherein the probabilistic information generator updates the probabilistic information a predetermined number of times that the read out data is stored in the storage unit.

13. The memory system of claim 12, wherein the probabilistic information generator updates the probabilistic information while the read out data is read from the memory device.

14. The memory system of claim 12, wherein a previously read out data stored in the storage unit is replaced with a currently read out data.