AUTOMATIC PIPELINING OF NOC CHANNELS TO MEET TIMING AND/OR PERFORMANCE

• US 20150178435A1
• Filed: 12/19/2013
• Published: 06/25/2015
• Est. Priority Date: 12/19/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Netspeed Systems, Inc. (Intel Corporation)
• Inventors: KUMAR, Sailesh
• Granted Patent: US 9,158,882 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 15/173 using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
• CPC Class Codes: G06F 15/177 Initialisation or configuration control processor initialisation G06F9/4405
• CPC Class Codes: G06F 2111/02 CAD in a network environment, e.g. collaborative CAD or distributed simulation
• CPC Class Codes: G06F 2115/02 System on chip [SoC] design
• CPC Class Codes: G06F 2115/10 Processors
• CPC Class Codes: G06F 2117/10 Buffer insertion
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/18 Network design, e.g. design based on topological or interconnect aspects of utility systems, piping, heating ventilation air conditioning [HVAC] or cabling circuit design at the physical level G06F30/39; network planning tools for wireless communication networks H04W16/18
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

Systems and methods for automatically generating a Network on Chip (NoC) interconnect architecture with pipeline stages are described. The present disclosure includes example implementations directed to automatically determining the number and placement of pipeline stages for each channel in the NoC. Example implementations may also adjust the buffer at one or more routers based on the pipeline stages and configure throughput for virtual channels.

Claims

1. A method, comprising:

generating a Network on Chip (NoC) comprising a plurality of channels and a plurality of routers, the NoC configured with one or more pipeline stages that are positioned at one or more of the plurality of channels in the NoC based on an associated system on chip (SoC) floorplan and a NoC topology;

for each of the plurality of channels in the NoC, generating an output register for a corresponding one of the plurality of routers handling output for the each of the one or more channels in the NoC based on a setup time of the corresponding router and a timing path within the corresponding router.

3. The method of claim 1, further comprising:

determining a number of the one or more pipeline stages for each of the plurality of channels in the NoC based on a clock frequency between a pair of the plurality of routers associated with the each of the one or more channels and a length of the each of the one or more channels, and

generating the one or more pipeline stages for the each of the plurality of channels based on the number determined by the determining.

4. The method of claim 3, further comprising positioning each of the generated one or more pipeline stages for the each of the plurality of channels based on a wire delay of the each of the plurality of channels.

5. The method of claim 3, further comprising adjusting a buffer at each of the plurality of routers based on the number of the one or more pipeline stages between a pairing of the each of the plurality of routers with an adjacent one of the plurality of routers.

6. The method of claim 5, wherein adjusting the buffer at each of the plurality of routers is further based on a throughput requirement between the pairing of the each of the plurality of routers with the adjacent one of the plurality of routers.

7. The method of claim 6, further comprising sizing one or more virtual channels associated with the each of the plurality of routers based on the throughput requirement.

8. The method of claim 5, wherein each of the one or more pipeline stages is configured to be utilized as a buffer supplement, and wherein the adjusting the buffer at each of the plurality of routers is based on ones of the one or more pipeline stages utilized by the each of the plurality of routers as a buffer supplement.

2. (canceled)

9. A non-transitory computer readable storage medium storing instructions for executing a process, the instructions comprising:

generating a Network on Chip (NoC) comprising a plurality of channels and a plurality of routers, the NoC configured with one or more pipeline stages that are positioned at one or more of the plurality of channels in the NoC based on an associated system on chip (SoC) floorplan and a NoC topology;

for each of the plurality of channels in the NoC, generating an output register for a corresponding one of the plurality of routers handling output for the each of the one or more channels in the NoC based on a setup time of the corresponding router and a timing path within the corresponding router.

11. The non-transitory computer readable storage medium of claim 9, wherein the instructions further comprise:

determining a number of the one or more pipeline stages for each of the plurality of channels in the NoC based on a clock frequency between a pair of the plurality of routers associated with the each of the one or more channels and a length of the each of the one or more channels, and

generating the one or more pipeline stages for the each of the plurality of channels based on the number.

12. The non-transitory computer readable storage medium of claim 11, wherein the instructions further comprise positioning each of the generated one or more pipeline stages for the each of the plurality of channels based on a wire delay of the each of the plurality of channels.

13. The non-transitory computer readable storage medium of claim 11, wherein the instructions further comprise adjusting a buffer at each of the plurality of routers based on the number of the one or more pipeline stages between a pairing of the each of the plurality of routers with an adjacent one of the plurality of routers.

14. The non-transitory computer readable storage medium of claim 13, wherein adjusting the buffer at each of the plurality of routers is further based on a throughput requirement between the pairing of the each of the plurality of routers with the adjacent one of the plurality of routers.

15. The non-transitory computer readable storage medium of claim 14, wherein the instructions further comprise sizing one or more virtual channels associated with the each of the plurality of routers based on the throughput requirement.

16. The non-transitory computer readable storage medium of claim 13, wherein each of the one or more pipeline stages is configured to be utilized as a buffer supplement, and wherein the adjusting the buffer at each of the plurality of routers is based on ones of the one or more pipeline stages utilized by the each of the plurality of routers as a buffer supplement.

10. (canceled)

17. A method, comprising:

generating a Network on Chip (NoC) comprising a plurality of channels and a plurality of routers, the NoC configured with one or more pipeline stages that are positioned at one or more of the plurality of channels in the NoC based on a NoC topology within an associated SoC floorplan, length of channels from the NoC topology, clock frequency, and wire delay.