DEFECTIVE P-N JUNCTION FOR BACKGATED FULLY DEPLETED SILICON ON INSULATOR MOSFET

• US 20150179453A1
• Filed: 02/10/2015
• Published: 06/25/2015
• Est. Priority Date: 04/19/2013
• Status: Active Grant

• Current Assignee: Commissariat a L'Energie Atomique (AES Corporation), STMicroelectronics Incorporated (STMicroelectronics NV), Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Commissariat a L'Energie Atomique (AES Corporation), International Business Machines Corporation, STMicroelectronics Incorporated (STMicroelectronics NV)
• Inventors: CHENG, KANGGUO, GRENOUILLET, LAURENT, LIU, QING, DORIS, BRUCE B., KHAKIFIROOZ, ALI, LE TIEC, YANNICK, VINET, MAUD
• Granted Patent: US 9,373,507 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/2253 by ion implantation
• CPC Class Codes: H01L 21/761 PN junctions
• CPC Class Codes: H01L 21/7624 using semiconductor on insulator [SOI] technology H01L21/76297 takes precedence; manufacture of integrated circuits on insulating substrates H01L21/84; silicon on sapphire [SOS] technology H01L21/86
• CPC Class Codes: H01L 21/76243 using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0684 characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/78612 for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel

Abstract

Methods for semiconductor fabrication include forming a well in a semiconductor substrate. A pocket is formed within the well, the pocket having an opposite doping polarity as the well to provide a p-n junction between the well and the pocket. Defects are created at the p-n junction such that a leakage resistance of the p-n junction is decreased.

Claims

1. A method for semiconductor fabrication, comprising:

forming a material stack of at least one semiconductor layer and at least one dielectric layer on a bulk semiconductor substrate including a well region;

forming a pocket in the well region by ion implanting dopant through the material stack, wherein the pocket and the well region provide a p-n junction; and

creating defects at the p-n junction to reduce junction leakage.

2. The method as recited in claim 1, wherein creating defects includes creating defects as part of a same implantation used to form the pocket.

3. The method as recited in claim 1, wherein creating defects includes using a same mask used to form the pocket to apply a separate implantation.

4. The method as recited in claim 1, wherein creating defects includes performing a blanket implantation over the substrate.

5. The method as recited in claim 1, wherein the defects include end-of-range implant defects.

6. The method as recited in claim 1, wherein the defects include impurities that generate mid-gap states.

7. The method as recited in claim 1, wherein creating defects includes creating defects inside a depletion region associated with the p-n junction.

8. The method as recited in claim 1, wherein the well region is formed by implanting p-type or n-type dopants applied at an implant dose ranging from 10¹³/cm² to 10¹⁶/cm² with an implant energy ranging from 2 KeV to 200 KeV.

9. The method as recited in claim 8, wherein the pocket is formed by implanting p-type or n-type dopants applied at an implant dose ranging from 10¹³/cm² to 10¹⁶/cm² with an implant energy ranging from 5 KeV to 100 KeV.