LOW TEMPERATURE POLY-SILICON THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF

• US 20150179460A1
• Filed: 01/23/2014
• Published: 06/25/2015
• Est. Priority Date: 12/25/2013
• Status: Active Grant

• Current Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Original Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Inventors: Xu, Xiangyang
• Granted Patent: US 9,257,290 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 2029/42388 characterised by the shape of the insulating material
• CPC Class Codes: H01L 21/28158 Making the insulator
• CPC Class Codes: H01L 21/28229 by deposition of a layer, e.g. metal, metal compound or poysilicon, followed by transformation thereof into an insulating layer
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78675 with normal-type structure, e.g. with top gate

Abstract

The present disclosure relates to a low temperature poly-silicon thin film transistor which possesses electrical characteristics and reliability, and a method of manufacturing the thin film transistor. The low temperature poly-silicon thin film transistor at least includes a gate insulating layer which is a composite insulating layer comprising at least three dielectric layers, wherein the compactness of each dielectric layer successively increases in order of the formation sequence thereof in the manufacturing process. Because the relation between the compactness of each layer of the composite insulating layer and that of the others thereof is taken into account according to the present disclosure, each layer in the composite insulating layer of the low temperature poly-silicon thin film transistor manufactured by the method according to the present disclosure can have enhanced surface contact characteristic and thin film continuity. The thickness of each layer in the composite insulating layer is further considered, so that the parasitic capacitance can be effectively reduced, and thus the response rate of the transistor can be improved. Namely, by improving the GI film forming quality, the electrical characteristic and reliability of the low temperature poly-silicon thin film transistor can be improved

Claims

1. A method for manufacturing a low temperature poly-silicon thin film transistor, including the following steps:

providing an insulating substrate,

forming, on a buffer layer of the insulating substrate, at least one poly-silicon layer, on the surface of which a source region, a drain region, and a channel region of the low temperature poly-silicon thin film transistor are arranged,

conducting a plasma enhanced chemical vapor deposition (PECVD) procedure for at least three times to form at least three dielectric layers on the channel region successively, such that a composite gate insulating layer is formed, wherein the compactness of each dielectric layer increases in order of the formation sequence thereof in the manufacturing method, and

forming a gate electrode on the composite gate insulating layer.

2. The method according to claim 1, wherein the composite gate insulating layer comprises a first dielectric layer, a second dielectric layer, and a third dielectric layer, and

the first dielectric layer is made from SiO₂, the second dielectric layer is made from SiON, and the third dielectric layer is made from SiN_x.

3. The method according to claim 2, wherein the film thickness of the first dielectric layer is greater than those of both the second and the third dielectric layers.

4. The method according to claim 3, wherein the thickness of SiO₂ film of the first dielectric layer is in a range of from 1,000 to 1,500 angstroms, the thickness of SiON film of the second dielectric layer is in a range of from 100 to 1,000 angstroms, and the thickness of SiN_x film of the third dielectric layer is in a range of from 100 to 500 angstroms.

5. The method according to claim 1, wherein the formation of the poly-silicon layer includes the following steps:

performing a sputtering procedure so as to form an amorphous silicon layer on the surface of the insulating substrate, and

performing an annealing procedure so that the amorphous silicon layer re-crystallizes and forms the poly-silicon layer, wherein the annealing procedure includes an excimer laser annealing operation.

6. The method according to claim 1, wherein after the gate electrode is formed, an ion implantation procedure using the gate electrode as a mask is performed to form a source electrode and a drain electrode in the source region and the drain region respectively on the poly-silicon layer, and

after the ion implantation procedure, an activation procedure is performed to activate dopants in both the source electrode and the drain electrode.

7. A low temperature poly-silicon thin film transistor, at least including a gate insulating layer which is a composite insulating layer comprising at least three dielectric layers,

wherein the compactness of each dielectric layer successively increases in order of the formation sequence thereof in the manufacturing process.

8. The low temperature poly-silicon thin film transistor according to claim 7, wherein the gate insulating layer comprises a first dielectric layer, a second dielectric layer, and a third dielectric layer, and

the first dielectric layer is made from SiO₂, the second dielectric layer is made from SiON, and the third dielectric layer is made from SiN_x.

9. The low temperature poly-silicon thin film transistor according to claim 8, wherein the film thickness of the first dielectric layer is greater than those of both the second and the third dielectric layers.

10. The low temperature poly-silicon thin film transistor according to claim 9, wherein the thickness of SiO₂ film of the first dielectric layer is in a range of from 1,000 to 1,500 angstroms, the thickness of SiON film of the second dielectric layer is in a range of from 100 to 1,000 angstroms, and the thickness of SiN_x film of the third dielectric layer is in a range of from 100 to 500 angstroms.