Semiconductor Device and Method of Forming Fine Pitch RDL Over Semiconductor Die in Fan-Out Package

• US 20150179570A1
• Filed: 12/23/2013
• Published: 06/25/2015
• Est. Priority Date: 12/23/2013
• Status: Active Grant

• Current Assignee: Stats Chippac Limited
• Original Assignee: Stats Chippac Limited
• Inventors: Marimuthu, Pandi C., Lin, Yaojian, Choi, Won Kyoung, Shim, Il Kwon
• Granted Patent: US 9,721,922 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/561 Batch processing
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• CPC Class Codes: H01L 22/10 Measuring as part of the manufacturing process burn-in G01R31/2855
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14
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• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/68331 of passive members, e.g. die mounting substrate
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
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• CPC Class Codes: H01L 2224/024 Material of the insulating layers therebetween
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• CPC Class Codes: H01L 2224/48227 : connecting the wire to a bond pad of the item
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• CPC Class Codes: H01L 2224/83102 : using surface energy, e.g. capillary forces
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• CPC Class Codes: H01L 2224/92 : Specific sequence of method steps
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• CPC Class Codes: H01L 2224/92125 : the second connecting process involving a layer connector
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• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/00 : Details of semiconductor or other solid state devices H01L25/00 takes precedence ; structural arrangements for testing or measuring during manufacture or treatment, or for reliability measurements H01L22/00; arrangements for connecting or disconnecting semiconductor or solid-state bodies, or methods related thereto H01L24/00; finger print sensors G06V40/12
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
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• CPC Class Codes: H01L 23/5384 : Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
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• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
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• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
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Abstract

A semiconductor device has a first conductive layer including a plurality of conductive traces. The first conductive layer is formed over a substrate. The conductive traces are formed with a narrow pitch. A first semiconductor die and second semiconductor die are disposed over the first conductive layer. A first encapsulant is deposited over the first and second semiconductor die. The substrate is removed. A second encapsulant is deposited over the first encapsulant. A build-up interconnect structure is formed over the first conductive layer and second encapsulant. The build-up interconnect structure includes a second conductive layer. A first passive device is disposed in the first encapsulant. A second passive device is disposed in the second encapsulant. A vertical interconnect unit is disposed in the second encapsulant. A third conductive layer is formed over second encapsulant and electrically connected to the build-up interconnect structure via the vertical interconnect unit.

Claims

1. A method of making a semiconductor device, comprising:

providing a substrate;

forming a first conductive layer over the substrate;

disposing a semiconductor die over the first conductive layer;

disposing a first encapsulant over the semiconductor die;

removing the substrate;

disposing a second encapsulant over the first encapsulant; and

forming an interconnect structure over the first conductive layer and second encapsulant.

2. The method of claim 1, further including disposing a first passive device in the first encapsulant.

3. The method of claim 2, further including disposing a second passive device in the second encapsulant.

4. The method of claim 1, further including:

forming a first insulating layer over the substrate;

forming a second insulating layer over the first conductive layer; and

forming a second conductive layer over the second insulating layer.

5. The method of claim 4, further including removing a portion of the first insulating layer to expose the first conductive layer.

6. The method of claim 1, further including disposing an interconnect unit including a conductive via in a peripheral region of the semiconductor die.

7. A method of making a semiconductor device, comprising:

providing a first conductive layer;

disposing a first semiconductor die over the first conductive layer;

disposing a first encapsulant over the first semiconductor die; and

forming an interconnect structure over the first conductive layer opposite the first semiconductor die.

8. The method of claim 7, further including disposing a second semiconductor die over the first conductive layer.

9. The method of claim 7, further including forming a second conductive layer over the first encapsulant.

10. The method of claim 7, further including disposing a passive device in a peripheral region of the first semiconductor die.

11. The method of claim 10, further including depositing a second encapsulant over the passive device.

12. The method of claim 7, further including:

disposing an interconnect structure in a peripheral region of the first semiconductor die;

depositing a second encapsulant over the first semiconductor die and interconnect structure; and

removing a portion of the second encapsulant to expose the interconnect structure.

13. The method of claim 7, further including forming a composite interconnect structure over the first semiconductor die.

14. A semiconductor device, comprising:

a first conductive layer including a plurality of first conductive traces;

a first semiconductor die disposed over a first surface of the first conductive layer; and

a second conductive layer including a plurality of second conductive traces disposed over a second surface of the first conductive layer opposite the first surface of the first conductive layer, wherein a pitch of the first conductive traces is less than a pitch of the second conductive traces.

15. The semiconductor device of claim 14, further including:

a first encapsulant deposited over the first semiconductor die; and

a passive device disposed in the first encapsulant.

16. The semiconductor device of claim 15, further including:

a second encapsulant deposited around the first encapsulant; and

a second passive device disposed in the second encapsulant.

17. The semiconductor device of claim 14, further including a third conductive layer formed over the first semiconductor die opposite the first conductive layer.

18. The semiconductor device of claim 14, further including a second semiconductor die disposed over the first conductive layer.

19. The semiconductor device of claim 14, wherein the first conductive layer is formed over a temporary substrate and the temporary substrate is removed after the first semiconductor die is disposed over the first conductive layer.

20. A semiconductor device, comprising:

a first conductive layer;

a first semiconductor die disposed over the first conductive layer; and

an interconnect structure formed over the first conductive layer opposite the first semiconductor die.

21. The semiconductor device of claim 20, further including a second semiconductor die disposed over the first conductive layer.

22. The semiconductor device of claim 20, further including:

an encapsulant deposited around the first semiconductor die; and

a conductive via disposed in the encapsulant.

23. The semiconductor device of claim 22, further including a second conductive layer formed over the encapsulant and electrically connected to the conductive via.

24. The semiconductor device of claim 20, wherein the interconnect structure includes:

a second conductive layer;

an insulating layer formed over the second conductive layer; and

a third conductive layer formed over the insulating layer.

25. The semiconductor device of claim 20, wherein the first conductive layer is formed over a temporary substrate and the temporary substrate is removed after the first semiconductor die is disposed over the first conductive layer.