Three Dimensional NAND Device with Channel Located on Three Sides of Lower Select Gate and Method of Making Thereof

• US 20150179660A1
• Filed: 12/19/2013
• Published: 06/25/2015
• Est. Priority Date: 12/19/2013
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Yada, Shinsuke, Ogawa, Hiroyuki
• Granted Patent: US 9,449,983 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02238 silicon in uncombined form, i.e. pure silicon
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/42344 with at least one additional gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

A select gate transistor for a NAND device includes a select gate electrode having a first side, a second side, and top and a bottom, a semiconductor channel located adjacent to the first side, the second side and the bottom of the select gate electrode, and a gate insulating layer located between the channel and the first side, the second side and the bottom of the select gate electrode.

Claims

1. A select gate transistor for a NAND device, comprising:

a select gate electrode having a first side, a second side, a top and a bottom;

a semiconductor channel located adjacent to the first side, the second side and the bottom of the select gate electrode; and

a gate insulating layer located between the channel and the first side, the second side and the bottom of the select gate electrode.

2. The transistor of claim 1, wherein the first side of the select gate electrode is located opposite to the second side of the select gate electrode.

3. The transistor of claim 2, wherein the select gate electrode comprises a metal or metal alloy select gate electrode.

4. The transistor of claim 3, wherein the select gate electrode comprises a titanium nitride liner peripheral portion contacting the gate insulating layer, and a tungsten central portion contacting the titanium nitride liner peripheral portion.

5. The transistor of claim 2, wherein:

a first portion of the gate insulating layer contacts the first side of the select gate electrode, a second portion of the gate insulating layer contacts the second side of the select gate electrode, and a third portion of the gate insulating layer contacts the bottom of the select gate electrode; and

a first portion of the semiconductor channel contacts the first portion of the gate insulating layer, a second portion of the semiconductor channel contacts the second portion of the gate insulating layer, and a third portion of the semiconductor channel contacts the third portion of the gate insulating layer.

6. The transistor of claim 5, wherein:

the first portion of the semiconductor channel comprises a first semiconductor protrusion which extends perpendicular to a major surface of a substrate;

the second portion of the semiconductor channel comprises a second semiconductor protrusion which extends perpendicular to the major surface of the substrate; and

the third portion of the semiconductor channel comprises a semiconductor portion of the substrate or a semiconductor layer extending parallel to the major surface of the substrate under the select gate electrode.

7. The transistor of claim 6, wherein:

the substrate comprises a single crystal silicon substrate;

the first semiconductor protrusion comprises an epitaxial silicon rail having straight or tapered sidewalls;

the second semiconductor protrusion comprises an epitaxial silicon pillar having a cylindrical, truncated cone or inverse truncated cone shape having a smaller width than the first semiconductor protrusion; and

the third portion of the semiconductor channel comprises an upper portion of the substrate which connects the first semiconductor protrusion to the second semiconductor protrusion.

8. The transistor of claim 7, wherein:

the select gate transistor comprises a source side select gate transistor; and

the first semiconductor protrusion comprises a doped region which contacts a source line.

9. A monolithic three dimensional NAND string, comprising:

the source side select gate transistor of claim 8;

a NAND memory cell region comprising;

a semiconductor channel which extends perpendicular to the major surface of the substrate, wherein a bottom portion of the semiconductor channel contacts the second semiconductor protrusion;

at least one memory film located adjacent to the semiconductor channel; and

a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate, wherein the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level;

a drain side select transistor located over the NAND memory cell region; and

a drain line which electrically contacts an upper portion of the semiconductor channel.

10. The monolithic three dimensional NAND string of claim 9, wherein the at least one memory film comprises a blocking dielectric, a charge trapping layer or floating gate, and a tunnel dielectric, and the memory film is located between the semiconductor channel and the plurality of control gate electrodes.

11. The monolithic three dimensional NAND string of claim 10, wherein:

the tunnel dielectric comprises a silicon oxide layer which extends perpendicular to the major surface of the substrate;

the charge trapping layer comprises a silicon nitride layer which extends perpendicular to the major surface of the substrate and which contacts the tunnel dielectric; and

the blocking dielectric comprises a first silicon oxide layer which extends perpendicular to the major surface of the substrate and which contacts the charge trapping layer, and a second metal oxide layer which has a plurality of clam shape regions, each of which surrounds a respective one of the plurality of control gate electrodes.

12. A memory block, comprising:

an array comprising at least one row of monolithic three dimensional NAND strings of claim 9;

a first dielectric filled trench located on a first side of the array; and

a second dielectric filled trench located on a second side of the array opposite to the first side of the array.

13. The memory block of claim 12, wherein:

the at least one row of monolithic three dimensional NAND strings comprises at least a 4×

4 array of monolithic three dimensional NAND strings of claim 9;

the source line is located in the first dielectric filled trench;

a second source line is located in the second dielectric filled trench;

a plurality of drain lines are located over the array;

the first control gate electrode is continuous in the array;

the second control gate electrode is continuous in the array;

the select gate electrode is continuous in the array; and

all of the monolithic three dimensional NAND strings in the array are configured to be erased together in the same erase step.

14. A memory block, comprising:

a substrate;

an array comprising at least one row of monolithic three dimensional NAND strings;

a first dielectric filled trench located on a first side of the array;

a second dielectric filled trench located on a second side of the array opposite to the first side of the array;

a first source line located in the first dielectric filled trench;

a second source line located in the second dielectric filled trench; and

a plurality of drain lines located over the array;

wherein;

each NAND string comprises a semiconductor channel, a tunnel dielectric located adjacent to an end portion of the semiconductor channel, a charge storage region located adjacent to the tunnel dielectric, a blocking dielectric located adjacent to the charge storage region, a source side select gate electrode, a gate insulating layer, a drain side select gate electrode, and a plurality of control gate electrodes extending substantially parallel to a major surface of the substrate;

the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level;

the source side select gate electrode, the first control gate electrode and the second control gate electrode are continuous in the array;

a first portion of the gate insulating layer contacts a first side of the source side select gate electrode, a second portion of the gate insulating layer contacts a second side of the source side select gate electrode, and a third portion of the gate insulating layer contacts bottom of the source side select gate electrode; and

a first portion of the semiconductor channel contacts the first portion of the gate insulating layer, a second portion of the semiconductor channel contacts the second portion of the gate insulating layer, and a third portion of the semiconductor channel contacts the third portion of the gate insulating layer.

15. The memory block of claim 14, wherein:

the array comprises at least a 4×

4 array of monolithic three dimensional NAND strings;

the first portion of the semiconductor channel comprises a first semiconductor protrusion which extends perpendicular to the major surface of the substrate;

the second portion of the semiconductor channel comprises a second semiconductor protrusion which extends perpendicular to the major surface of the substrate; and

the third portion of the semiconductor channel comprises a semiconductor portion of the substrate or a semiconductor layer extending parallel to the major surface of the substrate under the control gate electrode.

16. The transistor of claim 15, wherein:

the substrate comprises a single crystal silicon substrate;

the end portion of the semiconductor channel, the tunnel dielectric, the charge storage region and the blocking dielectric extend through the first and through the second device levels;

the end portion of the semiconductor channel comprises a semiconductor pillar or hollow cylinder which extends perpendicular to the major surface of the substrate;

the first semiconductor protrusion comprises an epitaxial silicon rail having straight, inverse tapered or tapered sidewalls;

the second semiconductor protrusion comprises an epitaxial silicon pillar having a cylindrical, truncated cone or inverse truncated cone shape having a smaller width than the first semiconductor protrusion; and

the third portion of the semiconductor channel comprises an upper portion of the semiconductor substrate which connects the first semiconductor protrusion to the second semiconductor protrusion.

17. The memory block of claim 16, wherein:

the plurality of drain lines extend in a bit line direction from the first dielectric filled trench to the second dielectric filled trench;

the source side select gate electrode, the first control gate electrode, and the second control gate electrode extend in a word line direction which is perpendicular to the bit line direction;

the array comprises first, second, third and fourth rows of NAND strings extending in the word line direction; and

the semiconductor channels in the first and the third rows of NAND strings are offset from respective semiconductor channels in the second and fourth rows of NAND strings.

18. The memory block of claim 17, wherein:

the first semiconductor protrusion in each of the first and the second rows of NAND strings comprises a doped region which contacts the first source line;

the first semiconductor protrusion in each of the third and the fourth rows of NAND strings comprises a doped region which contacts the second source line; and

the second semiconductor protrusion in each of the first, second, third and fourth rows of NAND strings contacts the respective end portion of the semiconductor channel in each of the first, second, third and fourth rows of NAND strings.

19. The memory block of claim 18, wherein:

the memory block contains a common control gate electrode in each of the plurality of device levels for the first second, third and fourth rows of NAND strings;

the source side select gate electrode comprises a common source side select gate electrode for the first second, third and fourth rows of NAND strings; and

all of the NAND strings in the array are configured to be erased together in the same erase step.

20. The memory block of claim 19, wherein:

the source side select gate electrode comprises a metal or metal alloy select gate electrode;

the semiconductor channel comprises a solid rod shaped channel or a hollow cylinder shaped channel;

the tunnel dielectric comprises a cylinder which surrounds the semiconductor channel;

the charge storage region comprises a cylinder which surrounds the tunnel dielectric;

the blocking dielectric comprises a cylinder which surrounds the charge storage region; and

the first and the second control gate electrodes comprise metal or metal alloy control gate electrodes which surround the blocking dielectric in each NAND string.

21. A method of making a semiconductor device, comprising:

forming a first semiconductor protrusion and a second semiconductor protrusion that extend perpendicular to a major surface of a substrate such that the first semiconductor protrusion is connected to the second semiconductor protrusion by a third semiconductor region which extends parallel to the major surface of the substrate;

forming a gate insulating layer over at least a first side of the first semiconductor protrusion, over at least a second side of the second semiconductor protrusion and over a top of the third semiconductor region; and

forming a gate electrode over the gate insulating layer between the first side of the first semiconductor protrusion, the second side of the second semiconductor protrusion and the top of the third semiconductor region.

22. The method of claim 21, wherein the semiconductor device comprises a select gate transistor of a NAND device and the gate electrode comprises a select gate electrode of the select gate transistor.

23. The method of claim 22, wherein the step of forming the first semiconductor protrusion and the second semiconductor protrusion comprises:

forming an epitaxial silicon layer over the major surface of the substrate which comprises a single crystal silicon substrate; and

patterning the epitaxial silicon layer to form the first semiconductor protrusion and the second semiconductor protrusion connected by the third semiconductor region which is located in the single crystal silicon substrate.

24. The method of claim 23, wherein:

the step of patterning the epitaxial silicon layer comprises forming a first mask portion and a second mask portion over the epitaxial silicon layer and etching portions of the epitaxial silicon layer that are not covered by the first mask portion and the second mask portion to form the first semiconductor protrusion covered by the first mask portion and the second semiconductor protrusion covered by the second mask portion;

the step of forming the gate insulating layer comprises oxidizing the first side of the first semiconductor protrusion, the second side of the second semiconductor protrusion and the top of the third semiconductor region without oxidizing tops of the first and the second semiconductor protrusions which are covered by the respective first and second mask portions; and

the step of forming the gate electrode comprises removing the first and the second mask portions, forming a metal or metal alloy layer over and between the first and the second semiconductor protrusions and planarizing the metal or metal alloy layer to expose the top of the first semiconductor protrusion and the top of the second semiconductor protrusion.

25. The method of claim 24, wherein:

the first semiconductor protrusion comprises an epitaxial silicon rail having straight or tapered sidewalls;

the second semiconductor protrusion comprises an epitaxial silicon pillar having a cylindrical, truncated cone or inverse truncated cone shape having a smaller width than the first semiconductor protrusion;

the step of forming the metal or metal alloy layer comprises forming a titanium nitride liner over and between the first and the second semiconductor protrusions and forming a tungsten layer over the titanium nitride liner; and

planarizing the metal or metal alloy layer comprises chemical mechanical polishing of the titanium nitride liner and the tungsten layer.

26. The method of claim 22, further comprising:

forming a stack of alternating layers of a first material and a second material over the select gate transistor, wherein the first material comprises an insulating material and the second material comprises a sacrificial material;

etching the stack to form at least one front side memory opening in the stack to expose the second protrusion;

forming a blocking dielectric in the memory opening;

forming a charge storage region over the blocking dielectric in the memory opening;

forming a tunnel dielectric over the charge storage region in the memory opening;

removing the blocking dielectric, the charge storage region and the tunnel dielectric from a bottom of the memory opening; and

forming a semiconductor layer in the memory opening in contact with the second semiconductor protrusion.

27. The method of claim 26, wherein the first semiconductor protrusion, the second semiconductor protrusion, the third semiconductor region, and the semiconductor layer form a continuous channel of a NAND string of the NAND device.

28. The method of claim 27, wherein the first material comprises silicon oxide and the second material comprises silicon nitride.

29. The method of claim 27, further comprising:

etching the stack to form a back side opening in the stack;

removing at least a portion of the second material layers through the back side opening to form back side recesses between the first material layers; and

forming metal or metal alloy control gates in the back side recesses through the back side opening.

30. The method of claim 29, further comprising forming an additional metal oxide blocking dielectric in the back side recesses through the back side opening, wherein the step of forming the control gates comprises forming the control gates over the additional metal oxide blocking dielectric in the back side recesses through the back side opening.

31. The method of claim 29, wherein:

the step of forming the back side opening comprises forming a back side trench which exposes the second semiconductor protrusion which has a rail shape and extends along the back side trench; and

the step of forming the control gates comprises forming a titanium nitride liner layer in the back side recesses, forming a tungsten layer over the titanium nitride layer to fill the back side recesses and at least a portion of the back side trench, and recessing the tungsten layer from the back side trench.

32. The method of claim 31, further comprising:

forming a doped semiconductor region in the second semiconductor protrusion through the back side trench;

forming an insulating layer on sidewalls and bottom of the back side trench after the step of recessing the tungsten layer;

removing the insulating layer from the bottom of the back side trench without removing the insulating layer from the sidewalls of the trench; and

forming a source line in the back side trench in contact with the doped semiconductor region in the first semiconductor protrusion.

33. The method of claim 32, further comprising forming a support column opening in the stack and filling the support column opening with an insulating support pillar prior to the step of removing at least a portion of the second material layers.

34. The method of claim 32, further comprising forming a second select gate transistor above the stack and forming drain line contacting a top of the semiconductor layer.

35. The method of claim 32, further comprising:

forming a plurality of additional second protrusions;

forming an additional first protrusion;

forming a second back side trench over the additional first protrusion;

forming a second source line in the second back side trench in contact with the additional first protrusion;

forming at least one row of front side memory openings between the back side trench and the second back side trench;

forming a blocking dielectric in each of the memory openings;

forming a charge storage region over the blocking dielectric in each of the memory openings;

forming a blocking dielectric over the charge storage region in each of the memory openings;

removing the blocking dielectric, the charge storage region and the tunnel dielectric from the bottom of each of the memory openings;

forming a semiconductor layer in each of the memory openings in contact with a respective one of the plurality of additional second semiconductor protrusions; and

forming a plurality of drain lines over the memory openings in contact with the semiconductor layer.

36. The method of claim 35, wherein forming the at least one row of front side memory openings comprises forming at least a 4×

4 array of front side memory openings.