COBALT-CONTAINING CONDUCTIVE LAYERS FOR CONTROL GATE ELECTRODES IN A MEMORY STRUCTURE

• US 20150179662A1
• Filed: 02/04/2015
• Published: 06/25/2015
• Est. Priority Date: 06/30/2010
• Status: Active Grant

• Current Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: MAKALA, Raghuveer S., MATAMIS, George, LEE, Yao-Sheng, ALSMEIER, Johann, SHARANGPANI, Rahul, KOKA, Sateesh, MIZUNO, Genta, TAKEGUCHI, Naoki, KANAKAMEDALA, Senaka Krishna
• Granted Patent: US 10,128,261 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/32133 by chemical means only
• CPC Class Codes: H01L 21/76841 Barrier, adhesion or liner layers
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/4958 with a multiple layer structure
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H01L 29/7889 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/00 EEPROM devices comprising charge-trapping gate insulators
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 43/35 : with cell select transistors, e.g. NAND

Abstract

A memory film and a semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulator layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulator layers, a metallic barrier material portion can be formed in each backside recess. A cobalt portion can be formed in each backside recess. Each backside recess can be filled with a cobalt portion alone, or can be filled with a combination of a cobalt portion and a metallic material portion including a material other than cobalt.

Claims

1. A three-dimensional memory device comprising:

a stack of alternating layers comprising insulator layers and electrically conductive layers and located over a substrate;

an opening extending through the stack;

a blocking dielectric, at least one charge storage element and a tunneling dielectric located within the opening; and

a semiconductor channel located within the opening, wherein each of the electrically conductive layers comprises at least a cobalt portion.

2. The three-dimensional memory device of claim 1, wherein the electrically conductive layers comprise:

a first control gate electrode located in a first device level; and

a second control gate electrode located in a second device level that is located below the first device level.

3. The three-dimensional memory device of claim 1, wherein each of the electrically conductive layers further comprises a metallic barrier material portion contacting an overlying insulator layer, an underlying insulator layer, and a sidewall of a blocking dielectric layer.

4. The three-dimensional memory device of claim 3, further comprising a backside contact structure extending through a backside contact trench in the stack, electrically isolated from the electrically conductive layers, and electrically shorted to the semiconductor channel.

5. The three-dimensional memory device of claim 4, wherein a proximal sidewall of each cobalt portion is laterally spaced from the blocking dielectric by a vertical portion of a respective metallic barrier material portion, and each cobalt portion is laterally recessed from the backside contact trench.

6. The three-dimensional memory device of claim 3, wherein each cobalt portion contacts a surface of a respective metallic barrier material portion.

7. The three-dimensional memory device of claim 6, wherein each cobalt portion contacts a pair of horizontal surfaces of the respective metallic barrier material portion and an outer sidewall of the respective metallic barrier material portion.

8. The three-dimensional memory device of claim 6, wherein each electrically conductive layer consists of a respective cobalt portion and a respective metallic barrier material portion.

9. The three-dimensional memory device of claim 6, wherein each of the electrically conductive layers further comprises a metallic material portion containing a material other than cobalt and contacting a respective cobalt portion.

10. The three-dimensional memory device of claim 9, wherein each metallic material portion is laterally spaced from a metallic barrier material portion located at a same level by a respective cobalt portion, and comprises tungsten or a tungsten alloy.

11. The three-dimensional memory device of claim 9, wherein each metallic material portion is vertically spaced from a metallic barrier material portion located at a same level by a respective cobalt portion.

12. The three-dimensional memory device of claim 9, wherein each metallic material portion contacts a pair of horizontal surfaces of a respective metallic barrier material portion located at a same level.

13. The three-dimensional memory device of claim 9, wherein each metallic material portion contacts a horizontal surface of an overlying dielectric layer and a horizontal surface of an underlying dielectric layer.

14. The three-dimensional memory device of claim 9, wherein each cobalt portion contacts a horizontal surface of an overlying dielectric layer and a horizontal surface of an underlying dielectric layer.

15. The three-dimensional memory device of claim 9, wherein each cobalt portion is laterally spaced from a vertical portion of a metallic barrier material portion located at a same level by a respective metallic material portion that comprises tungsten or a tungsten alloy.

16. The three-dimensional memory device of claim 1, wherein each of the electrically conductive layers comprises:

a metallic barrier material portion contacting an outer sidewall of the blocking dielectric;

a metallic material portion containing a material other than cobalt and contacting the metallic barrier material portion; and

a respective cobalt portion contacting horizontal surfaces of the metallic material portion and not contacting the metallic barrier material portion.

17. The three-dimensional memory device of claim 1, wherein each of the electrically conductive layers comprises:

a metallic barrier material portion contacting an outer sidewall of the blocking dielectric;

a cobalt material portion contacting the metallic barrier material portion; and

a metallic material portion containing a material other than cobalt contacting horizontal surfaces of the cobalt material portion and not contacting the metallic barrier material portion.

18. The three-dimensional memory device of claim 1, wherein each of the electrically conductive layers contacts surfaces of a backside blocking dielectric layer.

19. The three-dimensional memory device of claim 18, wherein each electrically conductive layer comprises a metallic barrier material portion contacting a backside blocking dielectric layer and a respective cobalt portion.

20. The three-dimensional memory device of claim 1, wherein:

the three-dimensional memory device comprises a vertical NAND device located in a device region; and

the electrically conductive layers comprise, or are electrically connected to a respective word line of the NAND device.

21. The three-dimensional memory device of claim 20, wherein:

the device region comprises;

a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate;

a plurality of charge storage regions, each charge storage region located adjacent to a respective one of the plurality of semiconductor channels; and

a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate;

the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level;

the electrically conductive layers in the stack are in electrical contact with the plurality of control gate electrode and extend from the device region to a contact region including the plurality of electrically conductive via connections; and

the substrate comprises a silicon substrate containing a driver circuit for the NAND device.

22. A method of manufacturing a three-dimensional memory device, comprising:

forming a stack of alternating layers comprising insulator layers and sacrificial material layers over a substrate;

forming an opening through the stack;

forming a blocking dielectric at a periphery of the opening;

forming at least one charge storage element over the blocking dielectric;

forming a tunneling dielectric over the at least one charge storage element;

forming a semiconductor channel over the tunneling dielectric in the opening;

forming backside recesses around the blocking dielectric by removing the sacrificial material layers; and

forming electrically conductive layers within the backside recesses, wherein each of the electrically conductive layers is formed by depositing at least a cobalt portion within a respective backside recess.

23. The method of claim 22, further comprising forming a metallic bather material portion in each backside recess prior to forming the cobalt portions.

24. The method of claim 23, further comprising forming a backside contact trench through the stack, wherein the backside recesses are formed by removing the sacrificial material layers through the backside contact trench.

25. The method of claim 24, wherein the metallic barrier material portions are formed by:

depositing a metallic barrier material layer in the backside recesses and on a sidewall of the backside contact trench; and

removing vertical portions of the metallic barrier material layer from the sidewall of the backside contact trench, wherein remaining portions of the metallic barrier material layer constitutes the metallic barrier material portions.

26. The method of claim 25, further comprising:

depositing a contiguous cobalt layer on the metallic barrier material layer; and

etching back portions of the contiguous cobalt layer from the backside contact trench prior to removing the vertical portions of the metallic barrier material layer, wherein each remaining portion of the contiguous cobalt layer constitutes the cobalt portions of the electrically conductive layers.

27. The method of claim 24, wherein each cobalt portion of the electrically conductive layers is formed on a surface of a respective metallic barrier material portion.

28. The method of claim 27, wherein each cobalt portion of the electrically conductive layers is formed on a pair of horizontal surfaces of the respective metallic barrier material portion and an outer sidewall of the respective metallic barrier material portion.

29. The method of claim 28, further comprising:

depositing a metallic barrier material layer in the backside recesses and on a sidewall of the backside contact trench;

depositing a contiguous cobalt layer on the metallic barrier material layer; and

removing vertical portions of the metallic barrier material layer and the contiguous cobalt layer from a sidewall of the backside contact trench, wherein remaining portions of the metallic barrier material layer constitute metallic barrier material portions, and remaining portions of the contiguous cobalt layer constitute the cobalt portions.

30. The method of claim 29, further comprising forming a metallic material portion comprising a material other than cobalt in a vacant portion of each backside recess.

31. The method of claim 30, wherein each metallic material portion is vertically and laterally spaced from a metallic barrier material portion located at a same level by a respective cobalt portion, and comprises tungsten or a tungsten alloy.

32. The method of claim 30, wherein each metallic material portion contacts a pair of horizontal surfaces of a metallic barrier material portion located at a same level.

33. The method of claim 29, wherein each electrically conductive layer consists of a respective cobalt portion and a metallic barrier material portion.

34. The method of claim 29, further comprising selectively depositing cobalt after formation of the metallic barrier material portions as a plurality structures vertically disjoined from one another, wherein each deposited portion of cobalt constitutes one of the cobalt portions.

35. The method of claim 29, further comprising:

depositing a metallic barrier material layer in the backside recesses and on a sidewall of the backside contact trench;

depositing a contiguous metallic material layer comprising a material other than cobalt; and

removing vertical portions of the metallic barrier material layer and the contiguous metallic material layer from a sidewall of the backside contact trench, wherein remaining portions of the metallic barrier material layer constitute metallic barrier material portions, and remaining portions of the contiguous metallic material layer constitute metallic material portions.

36. The method of claim 35, wherein each cobalt portion is formed directly on a respective metallic material portion located at a same level.

37. The method of claim 22, wherein the electrically conductive layers are formed directly on horizontal surfaces of the insulating layers and an outer sidewall of the blocking dielectric.

38. The method of claim 22, further comprising:

forming a metallic barrier material layer in the backside recesses;

filling the backside recesses by depositing a disposable material layer on the metallic barrier material layer;

forming a metallic barrier material portion and a disposable material portion at each level of the of backside recesses by removing vertical portions of the disposable material layer and the metallic barrier material layer;

removing the disposable material portions; and

forming the cobalt portions over the respective metallic barrier material portions.

39. The method of claim 38, further comprising forming backside dielectric material layer in the backside recesses prior to forming the metallic barrier material layer, wherein the metallic barrier material layer is formed on the backside dielectric material layer.

40. The method of claim 22, wherein:

the three-dimensional memory device comprises a vertical NAND device formed in a device region; and

the electrically conductive layers comprise, or are electrically connected to a respective word line of the NAND device.

42. A three-dimensional memory device comprising:

a stack of alternating layers comprising insulator layers and electrically conductive layers and located over a substrate;

a memory opening extending through the stack; and

a memory film and a semiconductor channel located within the memory opening, wherein each of the electrically conductive layers comprises at least a cobalt portion.

41. The method of claim 42, wherein:

the device region comprises;

a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate;

a plurality of charge storage regions, each charge storage region located adjacent to a respective one of the plurality of semiconductor channels; and

a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate;

the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level;

the electrically conductive layers in the stack are in electrical contact with the plurality of control gate electrode and extend from the device region to a contact region including the plurality of electrically conductive via connections; and

the substrate comprises a silicon substrate containing a driver circuit for the NAND device.