DISPLAY DEVICE, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING DISPLAY DEVICE

• US 20150179680A1
• Filed: 05/15/2013
• Published: 06/25/2015
• Est. Priority Date: 06/15/2012
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Tsuno, Hitoshi, Nagasawa, Koichi
• Granted Patent: US 9,508,758 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/1262 with a particular formation, treatment or coating of the substrate
• CPC Class Codes: H05B 33/10 Apparatus or processes specially adapted to the manufacture of electroluminescent light sources
• CPC Class Codes: H05B 33/22 characterised by the chemical or physical composition or the arrangement of auxiliary dielectric or reflective layers
• CPC Class Codes: H10K 59/1201 Manufacture or treatment
• CPC Class Codes: H10K 59/121 characterised by the geometry or disposition of pixel elements
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs
• CPC Class Codes: H10K 59/1216 the pixel elements being capacitors
• CPC Class Codes: H10K 59/124 Insulating layers formed between TFT elements and OLED elements
• CPC Class Codes: H10K 59/131 Interconnections, e.g. wiring lines or terminals
• CPC Class Codes: H10K 59/1315 comprising structures specially adapted for lowering the resistance

Abstract

A display device according to the present disclosure includes: a transistor section that includes a gate insulating film, a semiconductor layer, and a gate electrode layer, the semiconductor layer being laminated on the gate insulating film, the gate electrode film being laminated on an opposite side to the semiconductor layer of the gate insulating film; a first capacitor section that includes a first metal film and a second metal film, the first metal film being disposed at a same level as wiring layers that are electrically connected to the semiconductor layer and is disposed over the transistor section, the second metal film being disposed over the first metal film with a first interlayer insulating film in between; and a display element that is configured to be controlled by the transistor section.

Claims

1. A display device comprising:

a transistor section that includes a gate insulating film, a semiconductor layer, and a gate electrode layer, the semiconductor layer being laminated on the gate insulating film, the gate electrode film being laminated on an opposite side to the semiconductor layer of the gate insulating film;

a first capacitor section that includes a first metal film and a second metal film, the first metal film being disposed at a same level as a wiring layer that is electrically connected to the semiconductor layer and is disposed over the transistor section, the second metal film being disposed over the first metal film with a first interlayer insulating film in between; and

a display element that is configured to be controlled by the transistor section.

2. The display device according to claim 1, further comprising a second capacitor section that is provided below the first capacitor section, wherein the second capacitor section includes an insulating film, a separate semiconductor film, and a metal film, the insulating film being disposed at a same level as the gate insulating film, the separate semiconductor film being disposed at a same level as the semiconductor layer, the metal film being disposed at a same level as the gate electrode layer.

3. The display device according to claim 1, wherein the wiring layer and the first metal film are integrally formed, the wiring layer being electrically connected to the semiconductor layer.

4. The display device according to claim 1, wherein the first capacitor section includes at least one recessed portion in a plane of the first capacitor section.

5. The display device according to claim 4, wherein a bottom of the recessed portion is in contact with the gate insulating film of the transistor section.

6. The display device according to claim 4, wherein a bottom of the recessed portion is in contact with a substrate on which the transistor section is provided.

7. The display device according to claim 4, wherein the recessed portion is formed over the second capacitor section, and the first metal film of the first capacitor is electrically connected to one electrode film of the second capacitor section.

8. The display device according to claim 4, further comprising a second interlayer insulating film that is provided over the transistor section and includes at least one through hole, wherein the first capacitor section is provided over the second interlayer insulating film, and the recessed portion is formed in the through hole.

9. The display device according to claim 4, wherein the second interlayer insulating film includes two or more through holes as the through hole, and the second interlayer insulating film differs in thickness between an adjacent portion to another through hole and a non-adjacent portion.

10. The display device according to claim 1, wherein the first interlayer insulating film is formed over the wiring layer.

11. The display device according to claim 1, wherein the first interlayer insulating film is configured of any one, or any two or more of silicon oxide, silicon nitride, polyimide, and an acrylic resin.

12. The display device according to claim 1, wherein the first interlayer insulating film has a layered structure including at least one layer that is configured of a high dielectric constant material.

13. The display device according to claim 12, wherein the high dielectric constant material is a material having a relative dielectric constant of 10 or more.

14. A semiconductor device comprising:

a transistor section that includes a gate insulating film, a semiconductor layer, and a gate electrode layer, the semiconductor layer being laminated on the gate insulating film, the gate electrode film being laminated on an opposite side to the semiconductor layer of the gate insulating film; and

a first capacitor section that includes a first metal film and a second metal film, the first metal film being disposed at a same level as a wiring layer that is electrically connected to the semiconductor layer and is disposed over the transistor section, the second metal film being disposed over the first metal film with a first interlayer insulating film in between.

15. The semiconductor device according to claim 14, further comprising a second capacitor section that is provided below the first capacitor section, wherein the second capacitor section includes an insulating film, a separate semiconductor film, and a metal film, the insulating film being disposed at a same level as the gate insulating film, the separate semiconductor film being disposed at a same level as the semiconductor layer, the metal film being disposed at a same level as the gate electrode layer.

16. The semiconductor device according to claim 14, wherein the wiring layer and the first metal film are integrally formed, the wiring layer being electrically connected to the semiconductor layer.

17. The semiconductor device according to claim 14, wherein the first interlayer insulating film is formed over the wiring layer.

18. The semiconductor device according to claim 14, wherein the first interlayer insulating film is configured of any one, or any two or more of silicon oxide, silicon nitride, polyimide, and an acrylic resin.

19. A method of manufacturing a display device, comprising:

forming a transistor section by laminating a gate electrode, a gate insulating film, and a semiconductor layer;

forming a first capacitor section by depositing, over the transistor section, a wiring layer and a first metal film, and by depositing, over the first metal film, a second metal film with a first interlayer insulating film in between, the wiring layer being electrically connected to the semiconductor layer, the first metal film being at a same level as the wiring layer; and

forming a display element that is configured to be controlled by the transistor section.

20. The method of manufacturing the display device according to claim 19, further comprising:

depositing a second interlayer insulating film after forming the transistor section; and

forming a through hole in the second interlayer insulating film.