METHOD FOR FABRICATING SEMICONDUCTOR DEVICE

• US 20150179748A1
• Filed: 12/23/2013
• Published: 06/25/2015
• Est. Priority Date: 12/23/2013
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Chang, Yu-Chun, Shih, Ping-Chia, Huang, Chi-Cheng, Huang, Chung-Che, Li, Kuo-Lung, Chou, Kun-I, Hsu, Chia-Cheng, Liu, Mu-Jia
• Granted Patent: US 9,412,851 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region

Abstract

A method for fabricating a semiconductor device includes forming a patterned multi-layered dielectric film on a substrate; forming a patterned stack on the patterned multi-layered dielectric film so that an edge of the patterned multi-layered dielectric film is exposed from the patterned stack; forming a cover layer to cover a part of the substrate and expose the patterned stack and the exposed edge of the patterned multi-layered dielectric film; removing at least a part of the exposed edge of the patterned multi-layered dielectric film by using the cover layer and the patterned stack as an etching mask; and performing an ion implantation process by using the cover layer as an etching mask so as to form a doped region.

Claims

1. A method for fabricating a semiconductor device, comprising:

forming a patterned multi-layered dielectric film on a substrate;

forming a patterned stack on the patterned multi-layered dielectric film, wherein an edge of the patterned multi-layered dielectric film is exposed from the patterned stack;

forming a cover layer to cover a part of the substrate and expose the patterned stack and the exposed edge of the patterned multi-layered dielectric film;

removing at least a part of the exposed edge of the patterned multi-layered dielectric film by using the cover layer and the patterned stack as an etching mask; and

performing an ion implantation process by using the cover layer as an etching mask so as to form a doped region.

2. The method according to claim 1, further comprising:

forming a patterned pad oxide on the substrate; and

forming the patterned stack on the patterned pad oxide.

3. The method according to claim 1, wherein the patterned multi-layered dielectric film comprises a bottom oxide layer, a middle nitride layer, and a top oxide layer.

4. The method according to claim 3, wherein the bottom oxide layer is exposed after removing the exposed edge of the patterned multi-layered dielectric film.

5. The method according to claim 1, wherein the patterned multi-layered dielectric film comprises an electron trapping layer.

6. The method according to claim 1, wherein a pad oxide is disposed between the substrate and the patterned stack.

7. The method according to claim 1, further comprising completely removing the edge of the patterned multi-layered dielectric film after performing the ion implantation process.

8. The method according to claim 1, further comprising forming a silicide at a surface of the doped region.

9. The method according to claim 1, wherein the patterned stack further comprises a conductive layer and a cap layer.

10. The method according to claim 9, further comprising forming a silicide at a top surface of the conductive layer.

11. The method according to claim 1, further comprising:

forming an interlayer dielectric to cover the patterned stack;

removing the interlayer dielectric until the patterned stack is exposed;

removing the patterned stack so as to form at least a trench surrounded by the interlayer dielectric;

sequentially forming a dielectric layer and a work function layer in the trench; and

filling up the trench with a conductive material.