Method and Contact Structure for Coupling a Doped Body Region to a Trench Electrode of a Semiconductor Device

• US 20150179752A1
• Filed: 12/20/2013
• Published: 06/25/2015
• Est. Priority Date: 12/20/2013
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Siemieniec, Ralf, Yip, Li Juin, Blank, Oliver
• Granted Patent: US 9,190,480 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/76841 Barrier, adhesion or liner layers
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor body has a first surface, a second opposing surface, an edge, an active device region, and an edge termination region. A trench extends from the first surface into the semiconductor body in the edge termination region and includes sidewalls and an insulated electrode. A first conductivity type doped region extends from the first surface into the semiconductor body in the edge termination region and has a planar outer surface along the first surface that adjoins the trench at a corner of the trench sidewall and the first surface and has a side surface extending from the corner along the trench sidewall. A first interconnect contacts the trench electrode. A second interconnect contacts the outer surface and the side surface. A contact couples the first doped region to the trench electrode and has a bottom surface coplanar with the first surface from a contact edge to the corner.

Claims

1. A semiconductor device, comprising:

a semiconductor body comprising a first surface, a second surface opposite the first surface, an edge extending between the first and second surfaces, an active device region spaced inward from the edge and comprising at least one active semiconductor device, and an edge termination region between the active device region and the edge;

a trench extending from the first surface into the semiconductor body in the edge termination region, the trench comprising sidewalls and an electrode insulated from the surrounding semiconductor body;

a first doped region of a first conductivity type extending from the first surface into the semiconductor body in the edge termination region, the first doped region having a planar outer surface disposed along the first surface that adjoins the trench at a corner of one of the trench sidewalls and the first surface and having a side surface extending from the corner along the trench sidewall;

a first interconnect contacting the trench electrode;

a second interconnect contacting the outer surface and the side surface of the first doped region; and

an edge region contact contacting the first and second interconnects and electrically coupling the first doped region to the trench electrode, the edge region contact having a bottom surface that is coplanar with the first surface from an edge of the edge region contact to the corner.

2. The semiconductor device of claim 1, wherein the second interconnect comprises at least one of titanium silicide and titanium.

3. The semiconductor device of claim 1, further comprising:

a second doped region of a second conductivity type that is opposite the first conductivity type, the second doped region adjoining the first doped region below the first doped region to form a p-n junction that extends beneath the first surface and terminates at the trench sidewall that adjoins the first doped region.

4. The semiconductor device of claim 3, wherein the p-n junction is spaced closer to the first surface adjacent the trench sidewall that adjoins the first doped region and spaced further apart from the first surface at a distance from the trench sidewall.

5. The semiconductor device of claim 1, wherein the first doped region comprises a contact region of a first conductivity type that is more heavily doped than a surrounding portion of the first doped region, the contact region arranged between the second interconnect and the surrounding portion of the first doped region.

6. The semiconductor device of claim 1, further comprising a plurality of trenches, wherein the planar surface of the first doped region extends between adjacent ones of the trenches.

7. The semiconductor device of claim 1, further comprising a dielectric layer on the first surface of the semiconductor body, wherein the edge region contact is disposed in a single opening in the dielectric layer over the first doped region and the trench electrode.

8. The semiconductor device of claim 7, wherein the dielectric layer is in the trench and insulates the electrode from the surrounding semiconductor body, and wherein a single opening forms a recess in the dielectric layer between the electrode and one of the trench sidewalls such that the edge region contact extends beneath the first surface in the recess.

9. The semiconductor device of claim 1, further comprising:

a source contact in the active device region electrically connected to a source region of the at least one semiconductor device;

wherein the source contact comprises platinum silicide, and

wherein the edge region contact does not comprise platinum silicide.

10. A method of forming a semiconductor device in a semiconductor body comprising a first surface, a second surface opposite the first surface, an edge extending between the first and second surfaces, an active device region spaced inward from the edge and comprising at least one active semiconductor device, and an edge termination region between the active device region and the edge, the method comprising:

forming a trench extending from the first surface into the semiconductor body in the edge termination region, the trench comprising sidewalls and an electrode insulated from the surrounding semiconductor body;

forming a first doped region of a first conductivity type extending from the first surface into the semiconductor body in the edge termination region, the first doped region having a planar surface disposed along the first surface that adjoins one of the trench sidewalls at a corner of the trench sidewall and the first surface and a side surface extending from the corner along the trench sidewall;

forming a first interconnect contacting the trench electrode;

forming a second interconnect contacting the outer surface and the side surface of the first doped region; and

forming an edge region contact adjacent to the first and second interconnects and electrically coupling the first doped region to the trench electrode, the edge region contact having a bottom surface that is coplanar with the first surface from an edge of the edge region contact to the corner.

11. The method of claim 10, further comprising,

masking the edge termination region;

and

etching a contact groove into the semiconductor body in the active device region while the edge termination region is masked such that the first doped region is protected from the etching of the contact groove and maintains a planar surface disposed along the first surface that adjoins one of the trench sidewalls at a corner of the trench sidewall and the first surface.

12. The method of claim 10, wherein forming the second interconnect comprises depositing at least one of titanium silicide and titanium.

13. The method of claim 10, further comprising:

forming a second doped region of a second conductivity type that is opposite the first conductivity type, the second doped region adjoining the first doped region below the first doped region to form a p-n junction that extends beneath the first surface and terminates at the trench sidewall that adjoins the first doped region.

14. The method of claim 10, further comprising:

implanting dopants of the a first conductivity type in the first doped region to form a contact region that is more heavily doped than a surrounding portion of the first doped region, the contact region arranged between the second interconnect and the surrounding portion of the first doped region.

15. The method of claim 10, further comprising:

forming a plurality of trenches, wherein the planar surface of the first doped region extends between adjacent ones of the trenches.

16. The method of claim 10, further comprising:

forming a dielectric layer on the first surface of the semiconductor body;

etching a single opening in the dielectric layer over the first doped region and the trench electrode; and

forming the edge region contact in the opening.

17. The method of claim 16, wherein forming the first interconnect comprises depositing a conductive material on top side and sidewall portions of the electrode that are exposed from the dielectric layer, and wherein forming the second interconnect comprises depositing the conductive material on portions of the planar surface and side surface of the first doped region that are exposed from the dielectric layer.

18. The method of claim 17, wherein the dielectric layer is formed in the trench and insulates the electrode from the surrounding semiconductor body, wherein etching the single opening comprises forming a recess in the dielectric layer beneath the first surface between the electrode and one of the trench sidewalls, and wherein forming the edge region contact comprises depositing polysilicon over the first interconnect, the second interconnect and in the recess.

19. The method of claim 10, further comprising:

forming a source contact in the active device region electrically connected to a source region of the at least one semiconductor device;

forming an isolation layer in the edge termination region over the edge region contact;

providing a metal containing layer over the source contact; and

forming a metal silicide structure in the source contact without forming metal silicide in the edge region contact.

20. The method of claim 19, wherein the metal containing comprises platinum, and wherein the metal silicide structure comprises platinum silicide, the method further comprising:

performing a high temperature drive-in process that causes platinum to diffuse from the metal silicide structure into the semiconductor body in the active device area.