SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF

• US 20150179776A1
• Filed: 02/24/2015
• Published: 06/25/2015
• Est. Priority Date: 04/22/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: ISOBE, Atsuo, SASAKI, Toshinari, SASAGAWA, Shinya, ISHIZUKA, Akihiro
• Granted Patent: US 10,079,295 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02667 Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

An insulating layer is provided with a projecting structural body, and a channel formation region of an oxide semiconductor layer is provided in contact with the projecting structural body, whereby the channel formation region is extended in a three dimensional direction (a direction perpendicular to a substrate). Thus, it is possible to miniaturize a transistor and to extend an effective channel length of the transistor. Further, an upper end corner portion of the projecting structural body, where a top surface and a side surface of the projecting structural body intersect with each other, is curved, and the oxide semiconductor layer is formed to include a crystal having a c-axis perpendicular to the curved surface.

Claims

1. A method for manufacturing a semiconductor device, comprising:

forming an insulating layer including a projecting structural body that includes a curved surface in an upper end corner portion where a top surface of the projecting structural body and a side surface of the projecting structural body intersect with each other;

forming an oxide semiconductor layer in contact with at least a part of the top surface and the side surface while heat treatment is performed;

forming a source electrode and a drain electrode adjacent to the oxide semiconductor layer;

forming a gate insulating layer over the oxide semiconductor layer; and

forming a gate electrode over the gate insulating layer to cover at least a part of the top surface and the side surface.

2. The method for manufacturing a semiconductor device, according to claim 1,

wherein the heat treatment is performed at a temperature higher than or equal to 400°

C., and

wherein the oxide semiconductor layer is formed so that the oxide semiconductor layer includes a crystal having a c-axis substantially perpendicular to the curved surface.

3. The method for manufacturing a semiconductor device, according to claim 1,

wherein the insulating layer is etched to form the projecting structural body, and

wherein plasma treatment is performed on the projecting structural body in a rare gas atmosphere to form the curved surface.

4. The method for manufacturing a semiconductor device, according to claim 3, wherein the rare gas is argon.

5. The method for manufacturing a semiconductor device, according to claim 1,

wherein the insulating layer is etched with the use of a metal mask to form the projecting structural body, and

wherein the curved surface is formed, when the metal mask is removed by dry etching using a reactive gas.

6. The method for manufacturing a semiconductor device, according to claim 1, wherein the curved surface has a radius of curvature greater than or equal to 20 nm and less than or equal to 60 nm.

7. The method for manufacturing a semiconductor device, according to claim 1, wherein an average surface roughness of the curved surface is greater than or equal to 0.1 nm and less than 0.5 nm.

8. A method for manufacturing a semiconductor device, comprising:

forming an insulating layer including a projecting structural body that includes a curved surface in an upper end corner portion where a top surface of the projecting structural body and a side surface of the projecting structural body intersect with each other;

forming an oxide semiconductor layer having an amorphous state in contact with at least a part of the top surface and the side surface while heat treatment is performed at a temperature lower than 200°

C.;

heating the oxide semiconductor layer at a temperature higher than or equal to 450°

C. so that the oxide semiconductor layer includes a crystal having a c-axis substantially perpendicular to the curved surface;

forming a source electrode and a drain electrode adjacent to the oxide semiconductor layer;

forming a gate insulating layer over the oxide semiconductor layer; and

forming a gate electrode over the gate insulating layer to cover at least a part of the top surface and the side surface.

9. The method for manufacturing a semiconductor device, according to claim 8,

wherein the insulating layer is etched to form the projecting structural body, and

wherein plasma treatment is performed on the projecting structural body in a rare gas atmosphere to form the curved surface.

10. The method for manufacturing a semiconductor device, according to claim 9, wherein the rare gas is argon.

11. The method for manufacturing a semiconductor device, according to claim 8,

wherein the insulating layer is etched with the use of a metal mask to form the projecting structural body, and

wherein the curved surface is formed, when the metal mask is removed by dry etching using a reactive gas.

12. The method for manufacturing a semiconductor device, according to claim 8, wherein the curved surface has a radius of curvature greater than or equal to 20 nm and less than or equal to 60 nm.

13. The method for manufacturing a semiconductor device, according to claim 8, wherein an average surface roughness of the curved surface is greater than or equal to 0.1 nm and less than 0.5 nm.