CONFORMAL THIN FILM DEPOSITION OF ELECTROPOSITIVE METAL ALLOY FILMS

• US 20150179798A1
• Filed: 12/24/2013
• Published: 06/25/2015
• Est. Priority Date: 12/24/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Gilbert Dewey, Scott B. Clendenning
• Inventors: DEWEY, GILBERT, CLENDENNING, SCOTT B., ROMERO, PATRICIO PATO
• Granted Patent: US 9,455,150 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/28176 with a treatment, e.g. annealing, after the formation of the definitive gate conductor
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4975 being a silicide layer, e.g. TiSi2
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

The present disclosure relates to a method of forming a semiconductor. The method includes heating a substrate in a reaction chamber, supplying to the reaction chamber a first constituent including a metal borohydride wherein the metal borohydride includes at least one of: an alkaline earth metal, a transition metal, or a combination thereof; supplying to the reaction chamber a main-group hydride constituent; and depositing a metal compound on the substrate, wherein the metal compound comprises a) at least one of an alkaline earth metal a transition metal or a combination thereof, b) boron and c) optionally the main group alloying element.

Claims

1. A method of forming a semiconductor, comprising:

heating a substrate in a reaction chamber;

supplying to the reaction chamber a first constituent including a metal borohydride, wherein said metal borohydride includes at least one of;

an alkaline earth metal, a transition metal or a combination thereof;

supplying to the reaction chamber a main-group hydride constituent, wherein the hydride is a compound of hydrogen and a main group alloying element includes one or more elements selected from the following;

aluminum, gallium, silicon, germanium, tin, phosphorous, arsenic, antimony and combinations thereof; and

depositing a metal compound on the substrate, wherein the metal compound comprises a) the alkaline earth metal, the transition metal or the combination thereof, b) boron and c) optionally the main group alloying element.

2. The method of claim 1, further comprising depositing a gate oxide on the substrate surface and depositing the metal compound on the gate oxide to form a gate.

3. The method of claim 1, further comprising forming a source and drain in the substrate;

depositing a gate oxide on the substrate surface;

depositing a gate on the substrate surface;

depositing an interlaying dielectric on the substrate;

forming contact holes exposing one or more of the source, drain and gate; and

depositing the metal compound in the contact hole.

4. The method of claim 1, wherein the alkaline earth metal, transition metal or combination thereof is present in the range of 20 to 40 at % of the metal compound.

5. The method of claim 1, the first constituent comprises a metal complex having the formula:

(ML_x)_zD_y,

wherein M is the alkaline earth metal, transition metal or the combination thereof selected from Mg, Ca, Sr, Ba, Sc, Ti, Zr, Hf, V, Nb, Ta, Mo, Mn, Y, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb and Lu,

L is an anionic ligand of the following formula;

6. The method of claim 5, wherein the neutral coordinating ligand comprises a neutral coordinating ligand selected from the group consisting of alkenes, alkynes, ethers, sulfides, amines, nitriles, isonitriles, phosphines, phosphites, arsines, and stibines, wherein said ligand includes 1 to 10 carbon atoms.

7. The method of claim 1, wherein the first constituent comprises one of the following:

1) a metal aminodiboronate comprising a complex of a metal and one or more aminodiboronate ligands;

     2) a metal phosphinodiboronate comprising a complex of a metal and one or more phosphinodiboronate ligands; and

     3) a combination of the metal aminodiboronate and the metal phosphinodiboronate, wherein the metal is the alkaline earth metal, transition metal or the combination thereof.

8. The method of claim 1, wherein the metal compound includes one or more of the following:

a metal boride, a metal borosilicide, a metal borogermanide, a metal borogermasilicide and a metal borophosphide, wherein the metal is the alkaline earth metal, transition metal or combination thereof.

9. The method of claim 7, wherein the transition metal is selected from the group consisting of titanium, yttrium, gadolinium, erbium and combinations thereof.

10. The method of claim 1, wherein the metal compound comprises one of the following:

titanium borosilicide, titanium borophosphide, erbium boride, erbium borosilicide, erbium borophosphide, gadolinium borosilicide, gadolinium borophosphide, yttrium borosilicide and yttrium borophosphide.

11. The method of claim 1, wherein the substrate includes a fin extending from the substrate, the fin includes fin surfaces, and the substrate surface includes the fin surfaces.

12. The method of claim 1, wherein the substrate includes a nanowire, said nanowire includes surfaces forming a perimeter and said metal compound is deposited on said perimeter surfaces.

13. The method of claim 1, wherein the metal compound exhibits flatband voltage the range of −

0.5 V to −

1.0 V.

14. A transistor comprising:

a substrate including a surface;

a gate oxide disposed on the substrate surface, wherein the gate oxide comprises a dielectric constant of greater than 3.9;

a gate disposed on the gate oxide opposing the substrate surface, wherein the gate comprises a metal compound and the metal compound comprises a) at least one of;

an alkaline earth metal, a transition metal or a combination thereof, b) boron, and c) a main group alloying element selected from the following;

aluminum, gallium, silicon, germanium, tin, phosphorous, arsenic, antimony and combinations thereof, wherein the alkaline earth metal, transition metal or the combination thereof is present in the range of 20 to 40 at % percent and the compound includes less than 10% of impurities.

15. The transistor of claim 14, wherein the transition metal is selected from the group consisting of titanium, yttrium, gadolinium and erbium.

16. The transistor of claim 14, wherein the metal compound comprises one of the following:

titanium borosilicide, titanium borophosphide, erbium boride, erbium borosilicide, erbium borophosphide, gadolinium borosilicide, gadolinium borophosphide, yttrium borosilicide and yttrium borophosphide.

17. The transistor of claim 14, wherein the substrate includes a fin extending from the substrate, the fin includes fin surfaces, and the substrate surface includes the fin surfaces.

18. The transistor of claim 14, wherein the substrate includes a nanowire, said nanowire includes surfaces forming a perimeter and said metal compound is deposited on said perimeter surfaces.

19. The transistor of claim 14, wherein the metal compound exhibits flatband voltage the range of −

0.5 V to −

1.0V.

20. A semiconductor device, comprising:

a semiconductor substrate including a surface,

a source and a drain formed in the semiconductor surface;

a gate oxide disposed on the substrate surface, wherein the gate oxide comprises a dielectric constant of greater than 3.9;

a gate disposed on the gate oxide opposing the substrate surface; and

a contact deposited on one or more of the following;

the source, the drain and the gate, wherein the contact comprises a metal compound and the metal compound comprises a) at least one of;

an alkaline earth metal, a transition metal or a combination thereof, b) boron and c) a main group alloying element selected from the following;

aluminum, gallium, silicon, germanium, tin, phosphorous, arsenic, antimony and combinations thereof, wherein the alkaline earth metal, the transition metal or the combination thereof is present in the range of 20 to 40 at % percent and the compound includes less than 10% of impurities.

21. The semiconductor device of claim 20, wherein the transition metal is selected from the group consisting of titanium, yttrium, gadolinium and erbium.

22. The semiconductor device of claim 20, wherein the metal compound comprises one of the following:

titanium borosilicide, titanium borophosphide, erbium boride, erbium borosilicide, erbium borophosphide, gadolinium borosilicide, gadolinium borophosphide, yttrium borosilicide, yttrium borophosphide.

23. The semiconductor device of claim 20, wherein the substrate includes a fin extending from the substrate, the fin includes fin surfaces, and the substrate surface includes the fin surfaces.

24. The semiconductor device of claim 20, wherein the substrate includes a nanowire, said nanowire includes surfaces forming a perimeter and said metal compound is deposited on said perimeter surfaces.

25. The semiconductor device of claim 20, wherein the gate comprises the metal compound.

26. The semiconductor device of claim 20, wherein the metal compound exhibits flatband voltage the range of −

0.5 V to −

1.0V.

27. The semiconductor device of claim 20, wherein the semiconductor device is an integrated circuit.