MULTI-CORE COMPUTER PROCESSOR BASED ON A DYNAMIC CORE-LEVEL POWER MANAGEMENT FOR ENHANCED OVERALL POWER EFFICIENCY

• US 20150185816A1
• Filed: 09/23/2014
• Published: 07/02/2015
• Est. Priority Date: 09/23/2013
• Status: Active Grant

• Current Assignee: Cornell University
• Original Assignee: Cornell University
• Inventors: Albonesi, David H., Petrica, Paula, Izraelevitz, Adam M., Shoemaker, Christine A.
• Granted Patent: US 10,088,891 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/329 by task scheduling
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present disclosure provides methods and systems for managing power in a processor having multiple cores. In one implementation, a microarchitecture of a core within a general-purpose processor may include configurable lanes (horizontal slices through the pipeline) which can be powered on and off independently from each other within the core. An online optimization algorithm may determine within a reasonably small fraction of a time slice a combination of lanes within different cores of the processor to be powered on that optimizes performance under a power constraint budget for the workload running on the general-purpose processor. The online optimization algorithm may use an objective function based on response surface models constructed to fit to a set of sampled data obtained by running the workload on the general-purpose processor with multiple cores, without running the full workload. In other implementations, the power supply to lanes can be gated.

Claims

1. A method for managing power in a processor having multiple cores, wherein each core includes different partitioned power regions and each power region is partitioned into multiple lanes with each lane including processor components, comprising:

controlling power to the processor by independently turning on or off electrical power to the lanes, respectively, by turning on or off electrical power to components within each lane;

applying an optimization algorithm within a small fraction of a time slice to determine a combination of powered-on lanes within different cores of the processor that optimizes performance of the processor under a power constraint budget.

2. The method of claim 1, wherein:

a core of the multiple cores of the processor is partitioned into three power regions each comprising a plurality of pipeline stages;

a front end region, an execute region, and a memory region.

3. The method of claim 2, wherein:

the front end region includes a fetch, a decode, a reorder buffer, a rename, and a dispatch stage;

the execute region includes an issue queue, a register file, and a functional unit; and

the memory region includes a load queue and a store queue.

4. The method of claim 1, wherein:

a lane includes a sub-bank of an associated queue.

5. The method of claim 1, wherein:

a lane further includes a physical gating mechanism and a logical correctness mechanism.

6. The method of claim 5, wherein the physical gating mechanism includes a sleep transistor.

7. The method of claim 1, wherein the processor includes 32 cores.

8. The method of claim 1, wherein the time slice includes 100 ms.

9. The method of claim 1, wherein:

the time slice includes a configuration sampling phrase, a surrogate surface fitting phase, an optimization phrase, and a steady phrase;

the workload runs for a short sampling period during the configuration sampling phrase on the multiple cores of the processor to collect a set of sampled data;

a performance response surface model or a power response surface model is constructed to fit to the set of sampled data during the surrogate surface fitting phrase;

the online optimization algorithm using an objective function based on the response surface models determines the combination of powered lanes within different cores of the processor that optimizes performance under the power constraint budget for the workload during the optimization phrase;

the processor operates under the combination of powered lanes within different cores during the steady phase; and

the configuration sampling phrase, the surrogate surface fitting phase, and the optimization phrase together are within the reasonably small fraction of the time slice.

10. The method of claim 9, wherein:

the online optimization algorithm that optimizes performance under the power constraint budget for the workload is applied to a multivariate statistical experimental design with a set of responses and a set of factors;

a response is a sampled datum collected from the workload running for a short sampling period; and

a factor is a power region of a core.

11. The method of claim 10, wherein a response is a sampled throughput datum or a sampled power consumption datum collected from the workload running for a short sampling period.

12. The method of claim 10, wherein:

a core of the multiple cores of the processor is partitioned into three power regions each comprising a plurality of pipeline stages;

a front end region, an execute region, and a memory region; and

a factor is a front end region, an execute region, or a memory region.

13. The method of claim 12, wherein a response is a sampled datum collected from the workload runs for a short sampling period on a full factorial design of the factors, a Box-Behnken design of the factors, or a fractional factorial design of the factors.

14. The method of claim 13, wherein a response is a sampled datum collected from the workload running for a 1 ms sampling period.

15. The method of claim 13, wherein a response is an average of a set of sampled data collected for a plurality of subintervals of a sampling period.

16. The method of claim 9, wherein the performance response surface model or the power response surface model is constructed using a first order polynomial, a second order polynomial, or an interpolating model that places a Radial Basis Function (RBF) at each sampled datum.

17. The method of claim 9, wherein the online optimization algorithm incorporates a genetic algorithm.

18. A system having a computer processor having multiple cores, comprising:

a processor including multiple cores, each core being a computer processor core and being partitioned into multiple power regions, wherein each power region is further partitioned into multiple lanes;

a first storage storing a power constraint budget for a workload to be performed by the system;

a second storage storing the workload; and

a controller coupled to the first and second storages and the lanes of the cores, the controller operable to run an optimization algorithm to determine, within a reasonably small fraction of a time slice, a combination of powered-on lanes within different cores of the processor that optimizes performance under the power constraint budget for the workload, wherein components within each lane are powered on or off together under a control of the controller.

19. The system of claim 18, wherein:

a core of the multiple cores of the processor is partitioned into three power regions each comprising a plurality of pipeline stages;

a front end region, an execute region, and a memory region.

20. The system of claim 19, wherein:

the front end region includes a fetch, a decode, a reorder buffer, a rename, and a dispatch stage;

the execute region includes an issue queue, a register file, and a functional unit; and

the memory region includes a load queue and a store queue.

21. The system of claim 18, wherein:

a lane includes a sub-bank of an associated queue.

22. The system of claim 18, wherein:

a lane further includes a physical gating mechanism and a logical correctness mechanism.

23. The system of claim 22, wherein the physical gating mechanism includes a sleep transistor.

24. The system of claim 18, wherein the processor includes 32 cores.

25. The system of claim 18, wherein the time slice includes 100 ms.

26. The system of claim 18, wherein:

the time slice includes a configuration sampling phrase, a surrogate surface fitting phase, an optimization phrase, and a steady phrase;

the workload runs for a short sampling period during the configuration sampling phrase on the multiple cores of the processor to collect a set of sampled data;

a performance response surface model or a power response surface model is constructed to fit to the set of sampled data during the surrogate surface fitting phrase;

the online optimization algorithm using an objective function based on the response surface models determines the combination of powered lanes within different cores of the processor that optimizes performance under the power constraint budget for the workload during the optimization phrase;

the processor operates under the combination of powered lanes within different cores during the steady phase; and

the configuration sampling phrase, the surrogate surface fitting phase, and the optimization phrase together are within the reasonably small fraction of the time slice.

27. The system of claim 26, wherein:

the online optimization algorithm that optimizes performance under the power constraint budget for the workload is applied to a multivariate statistical experimental design with a set of responses and a set of factors;

a response is a sampled datum collected from the workload running for a short sampling period; and

a factor is a power region of a core.

28. The system of claim 27, wherein a response is a sampled throughput datum or a sampled power consumption datum collected from the workload running for a short sampling period.

29. The system of claim 27, wherein:

a core of the multiple cores of the processor is partitioned into three power regions each comprising a plurality of pipeline stages;

a front end region, an execute region, and a memory region; and

a factor is a front end region, an execute region, or a memory region.

30. The system of claim 29, wherein a response is a sampled datum collected from the workload running for a short sampling period on a full factorial design of the factors, a Box-Behnken design of the factors, or a fractional factorial design of the factors.

31. The system of claim 30, wherein a response is a sampled datum collected from the workload running for a 1 ms sampling period.

32. The system of claim 30, wherein a response is an average of a set of sampled data collected for a plurality of subintervals of a sampling period.

33. The system of claim 26, wherein the performance response surface model or the power response surface model is constructed using a first order polynomial, a second order polynomial, or an interpolating model that places a Radial Basis Function (RBF) at each sampled datum.

34. The system of claim 26, wherein the online optimization algorithm incorporates a genetic algorithm.

35. A method for managing power in a processor having multiple cores, wherein each core includes different partitioned power regions and each power region is partitioned into multiple lanes with each lane including processor components, comprising:

controlling power to the processor by independently controlling electrical power to the lanes, respectively;

controlling power levels supplied to components within each lane by a gating control; and

applying an optimization algorithm within a small fraction of a time slice to determine a combination of powered-on lanes within different cores of the processor that optimizes performance of the processor under a power constraint budget.

36. The method of claim 35, wherein the gating control in controlling electrical power to a lane is by clock gating, power gating, or voltage scaling.