Data Coherency Model and Protocol at Cluster Level
First Claim
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1. An apparatus for providing data coherency, comprising:
- a global persistent memory, wherein the global persistent memory is accessed using a protocol that includes input/output (I/O) semantics and memory semantics;
a reflected memory region, wherein the reflected memory region is a portion of the global persistent memory, and each node of a plurality of nodes maps the reflected memory region into a space that is not cacheable; and
a semaphore memory, wherein the semaphore memory provides a hardware assist for enforced data coherency.
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Abstract
An apparatus for providing data coherency is described herein. The apparatus includes a global persistent memory. The global persistent memory is accessed using a protocol that includes input/output (I/O) semantics and memory semantics. The apparatus also includes a reflected memory region. The reflected memory region is a portion of the global persistent memory, and each node of a plurality of nodes maps the reflected memory region into a space that is not cacheable. Further, the apparatus includes a semaphore memory. The semaphore memory provides a hardware assist for enforced data coherency.
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Citations
26 Claims
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1. An apparatus for providing data coherency, comprising:
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a global persistent memory, wherein the global persistent memory is accessed using a protocol that includes input/output (I/O) semantics and memory semantics; a reflected memory region, wherein the reflected memory region is a portion of the global persistent memory, and each node of a plurality of nodes maps the reflected memory region into a space that is not cacheable; and a semaphore memory, wherein the semaphore memory provides a hardware assist for enforced data coherency. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A system for providing a data coherency at a cluster level, comprising:
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a plurality of nodes, wherein the plurality of nodes include a software coherency mechanism; a global shared memory, wherein the global shared memory includes a message region, a semaphore region, a shared memory region; and one or more fabric memory controllers, wherein the one or more fabric memory controllers connects the plurality of nodes and provides a hardware assist for data coherency at the cluster level. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23)
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24. A method of data coherency at the cluster level, the method comprising:
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enabling a cacheable global memory, wherein the global memory is stored across a plurality of nodes; maintaining data coherency across the plurality of nodes; and implementing independent fault domains for each node of the plurality of nodes. - View Dependent Claims (25, 26)
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Specification