DISPLAY DEVICE

• US 20150187293A1
• Filed: 12/11/2014
• Published: 07/02/2015
• Est. Priority Date: 12/31/2013
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: YOO, Dukkeun, LEE, Wonho
• Granted Patent: US 9,570,020 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2300/0439 Pixel structures
• CPC Class Codes: G09G 2300/0452 Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
• CPC Class Codes: G09G 2310/0297 Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
• CPC Class Codes: G09G 2320/0242 Compensation of deficiencies in the appearance of colours
• CPC Class Codes: G09G 2320/0247 Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
• CPC Class Codes: G09G 3/3607 for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels display of colours in flat matrix panels other than liquid crystal displays G09G3/2003; grey scales specific for television H04N3/127
• CPC Class Codes: G09G 3/3614 Control of polarity reversal in general

Abstract

A disclosed display device includes a display panel including a plurality of data lines and a plurality of gate lines intersecting the data lines, and a pixel array comprising a plurality of pixels arranged in a matrix form, each pixel being divided into a subpixel having a first color, a subpixel having a second color, a subpixel having a third color, and a subpixel having a fourth color. Two adjacent subpixels in a horizontal line of the pixel array share one of the data lines. For at least one of the first, second, third, and fourth colors, subpixels having a same color are arranged in a hexagonal shape on four adjacent horizontal lines or a diamond shape on three adjacent horizontal lines of the pixel array.

Claims

1. A display device comprising:

a display panel including a plurality of data lines and a plurality of gate lines intersecting the data lines, and a pixel array comprising a plurality of pixels arranged in a matrix form, each pixel being divided into a subpixel having a first color, a subpixel having a second color, a subpixel having a third color, and a subpixel having a fourth color, wherein two adjacent subpixels in a horizontal line of the pixel array share one of the data lines;

a data driver configured to supply data voltages to the data lines;

a gate driver configured to sequentially supply a gate pulse to the gate lines; and

a timing controller configured to transmit data of an input image to the data driver and to control the data driver and the gate driver,

wherein, for at least one of the first, second, third, and fourth colors, subpixels having a same color are arranged in a hexagonal shape on four adjacent horizontal lines of the pixel array.

2. The display device of claim 1, wherein, in at least one of (4i+1)-th and (4i+4)-th horizontal lines of the pixel array, (4i+1)-th subpixels have the first color, (4i+2)-th subpixels have the second color, (4i+3)-th subpixels have the third color, and (4i+4)-th subpixels have the fourth color, where ‘

i’

is zero or a positive integer, and

wherein, in at least one of (4i+2)-th and (4i+3)-th horizontal lines of the pixel array, (4i+1)-th subpixels have the third color, (4i+2)-th subpixels have the fourth color, (4i+3)-th subpixels have the first color, and (4i+4)-th subpixels have the second color.

3. The display device of claim 2, wherein the data driver is configured to output the data voltages of a first polarity to (8i+1)-th, (8i+3)-th, (8i+6)-th, and (8i+8)-th data lines through (8i+1)-th, (8i+3)-th, (8i+6)-th, and (8i+8)-th output channels, respectively, and to output the data voltages of a second polarity to (8i+2)-th, (8i+4)-th, (8i+5)-th, and (8i+7)-th data lines through (8i+2)-th, (8i+4)-th, (8i+5)-th, and (8i+7)-th output channels, respectively,

wherein the data voltage from at least one of the data lines is configured to be sequentially charged first to a subpixel on the left of the data line and then to a subpixel on the right of the data line for at least one of the horizontal lines of the pixel array, and

wherein the data driver is configured to invert the polarity of the data voltages in a cycle of one horizontal period.

4. The display device of claim 3, wherein at least one of the (4i+1)-th and (4i+4)-th horizontal lines of the pixel array includes:

a first TFT configured to supply a first data voltage of the first polarity and the first color from a k-th data line to a first subpixel in response to a j-th gate pulse from a j-th gate line, where ‘

j’ and

‘

k’

are each a positive integer;

a second TFT configured to supply a first data voltage of the first polarity and the second color from the k-th data line to a second subpixel in response to a (j+1)-th gate pulse from a (j+1)-th gate line;

a third TFT configured to supply a first data voltage of the second polarity and the third color from a (k+1)-th data line to a third subpixel in response to the j-th gate pulse;

a fourth TFT configured to supply a first data voltage of the second polarity and the fourth color from the (k+1)-th data line to a fourth subpixel in response to the (j+1)-th gate pulse;

a fifth TFT configured to supply a second data voltage of the first polarity and the first color from a (k+2)-th data line to a fifth subpixel in response to the j-th gate pulse;

a sixth TFT configured to supply a second data voltage of the first polarity and the second color from the (k+2)-th data line to a sixth subpixel in response to the (j+1)-th gate pulse;

a seventh TFT configured to supply a second data voltage of the second polarity and the third color from a (k+3)-th data line to a seventh subpixel in response to the j-th gate pulse; and

an eighth TFT configured to supply a second data voltage of the second polarity and the fourth color from the (k+3)-th data line to an eighth subpixel in response to the (j+1)-th gate pulse.

5. The display device of claim 4, wherein at least one of the (4i+2)-th and (4i+3)-th horizontal lines of the display panel includes:

a ninth TFT configured to supply a third data voltage of the second polarity and the third color from the k-th data line to a ninth subpixel in response to a (j+2)-th gate pulse from a (j+2)-th gate line;

a tenth TFT configured to supply a third data voltage of the second polarity and the fourth color from the k-th data line to a tenth subpixel in response to a (j+3)-th gate pulse from a (j+3)-th gate line;

an eleventh TFT configured to supply a third data voltage of the first polarity and the first color from the (k+1)-th data line to an eleventh subpixel in response to the (j+2)-th gate pulse;

a twelfth TFT configured to supply a third data voltage of the first polarity and the third color from the (k+1)-th data line to a twelfth subpixel in response to the (j+3)-th gate pulse;

a thirteenth TFT configured to supply a fourth data voltage of the second polarity and third color from the (k+2)-th data line to a thirteenth subpixel in response to the (j+2)-th gate pulse;

a fourteenth TFT configured to supply a fourth data voltage of the second polarity and the fourth color from the (k+2)-th data line to a fourteenth subpixel in response to the (j+3)-th gate pulse;

a fifteenth TFT configured to supply a fourth data voltage of the first polarity and the first color from the (k+3)-th data line to a fifteenth subpixel in response to the (j+2)-th gate pulse; and

a sixteenth TFT configured to supply a fourth data voltage of the first polarity and the second color from the (k+3)-th data line to an sixteenth subpixel in response to the (j+3)-th gate pulse.

6. The display device of claim 2, wherein the data driver is configured to output the data voltages of a first polarity to (4i+1)-th and (4i+2)-th data lines through (4i+1)-th and (4i+2)-th output channels, respectively, and to output the data voltages of a second polarity to (4i+3)-th and (4i+4)-th data lines through (4i+3)-th and (4i+4)-th output channels, respectively,

wherein the data voltage from at least one of the data lines is sequentially charged first to a subpixel on the left of the data line and then to a subpixel on the right of the data line for at least one of the horizontal lines of the pixel array, and

wherein the data driver is configured to invert the polarity of the data voltages in a cycle of one horizontal period.

7. The display device of claim 6, wherein at least one of the (4i+1)-th and (4i+4)-th horizontal lines of the pixel array includes:

a first TFT configured to supply a first data voltage of the first polarity and the first color from a k-th data line to a first subpixel in response to a j-th gate pulse from a j-th gate line, where ‘

j’ and

‘

k’

are each a positive integer;

a second TFT configured to supply a first data voltage of the first polarity and the second color from the k-th data line to a second subpixel in response to a (j+1)-th gate pulse from a (j+1)-th gate line;

a third TFT configured to supply a first data voltage of the first polarity and the third color from a (k+1)-th data line to a third subpixel in response to the j-th gate pulse;

a fourth TFT configured to supply a first data voltage of the first polarity and the fourth color from the (k+1)-th data line to a fourth subpixel in response to the (j+1)-th gate pulse;

a fifth TFT configured to supply a first data voltage of the second polarity and the first color from a (k+2)-th data line to a fifth subpixel in response to the j-th gate pulse;

a sixth TFT configured to supply a first data voltage of the second polarity and the second color from the (k+2)-th data line to a sixth subpixel in response to the (j+1)-th gate pulse;

a seventh TFT configured to supply a first data voltage of the second polarity and the third color from a (k+3)-th data line to a seventh subpixel in response to the j-th gate pulse; and

an eighth TFT configured to supply a first data voltage of the second polarity and the fourth color supplied through the (k+3)-th data line to an eighth subpixel in response to the (j+1)-th gate pulse.

8. The display device of claim 7, wherein at least one of the (4i+2)-th and (4i+3)-th horizontal lines of the pixel array includes:

a ninth TFT configured to supply a second data voltage of the second polarity and the third color from the k-th data line to a ninth subpixel in response to a (j+2)-th gate pulse from a (j+2)-th gate line;

a tenth TFT configured to supply a second data voltage of the second polarity and the fourth color from the k-th data line to a tenth subpixel in response to a (j+3)-th gate pulse from a (j+3)-th gate line;

an eleventh TFT configured to supply a second data voltage of the second polarity and the first color from the (k+1)-th data line to an eleventh subpixel in response to the (j+2)-th gate pulse;

a twelfth TFT configured to supply a second data voltage of the second polarity and the second color from the (k+1)-th data line to a twelfth subpixel in response to the (j+3)-th gate pulse;

a thirteenth TFT configured to supply a second data voltage of the first polarity and the third color from the (k+2)-th data line to a thirteenth subpixel in response to the (j+2)-th gate pulse;

a fourteenth TFT configured to supply a second data voltage of the first polarity and the fourth color from the (k+2)-th data line to a fourteenth subpixel in response to the (j+3)-th gate pulse;

a fifteenth TFT configured to supply a second data voltage of the first polarity and the first color from the (k+3)-th data line to a fifteenth subpixel in response to the (j+2)-th gate pulse; and

a sixteenth TFT configured to supply a second data voltage of the first polarity and the second color from the (k+3)-th data line to a sixteenth subpixel in response to the (j+3)-th gate pulse.

9. A display device of claim 1, wherein the four subpixels of each of the pixels are disposed in two adjacent horizontal lines of the pixel array, either with three of the four subpixels disposed in one of the two adjacent horizontal lines and the other subpixel in the other of the two adjacent horizontal lines, or with two of the subpixels disposed in each of the two adjacent horizontal lines.

10. A display device comprising:

a display panel including a plurality of data lines and a plurality of gate lines intersecting the data lines, and a pixel array comprising a plurality of pixels arranged in a matrix form, each pixel being divided into a subpixel having a first color, a subpixel having a second color, a subpixel having a third color, and a subpixel having a fourth color, wherein two adjacent subpixels in a horizontal line of the pixel array share one of the data lines;

a data driver configured to supply data voltages to the data lines;

a gate driver configured to sequentially supply a gate pulse to the gate lines; and

a timing controller configured to transmit data of an input image to the data driver and to control the data driver and the gate driver,

wherein, for at least one of the first, second, third, and fourth colors, subpixels having a same color are arranged in a diamond shape on three adjacent horizontal lines of the pixel array.

11. The display device of claim 10, wherein, in at least one of odd-numbered horizontal lines of the pixel array, (4i+1)-th subpixels have the first color, (4i+2)-th subpixels have the second color, (4i+3)-th subpixels have the third color, and (4i+4)-th subpixels have the fourth color, where ‘

i’

is zero or a positive integer, and

wherein, in at least one of even-numbered horizontal lines of the pixel array, (4i+1)-th subpixels have the third color, (4i+2)-th subpixels have the fourth color, (4i+3)-th subpixels have the first color, and (4i+4)-th subpixels have the second color.

12. The display device of claim 11, wherein the data driver is configured to output the data voltages of a first polarity to odd-numbered data lines through odd-numbered output channels, respectively, and to output the data voltages of a second polarity to even-numbered data lines through even-numbered output channels, respectively,

wherein the data voltage from at least one of the odd-numbered data lines is configured to be sequentially charged first to a subpixel on the left of the odd-numbered data line and then to a subpixel on the right of the data line for at least one of the horizontal lines of the pixel array, and

wherein the data driver is configured to invert the polarity of the data voltages in a cycle of one horizontal period.

13. The display device of claim 12, wherein at least one of the odd numbered horizontal lines of the pixel array includes:

a first TFT configured to supply a first data voltage of the first polarity and the first color from a k-th data line to a first subpixel in response to a j-th gate pulse from a j-th gate line, where ‘

j’ and

‘

k’

are each a positive integer;

a second TFT configured to supply a first data voltage of the first polarity and the second color from the k-th data line to a second subpixel in response to a (j+1)-th gate pulse from a (j+1)-th gate line;

a third TFT configured to supply a first data voltage of the second polarity and the third color from a (k+1)-th data line to a third subpixel in response to the j-th gate pulse;

a fourth TFT configured to supply a first data voltage of the second polarity and the fourth color from the (k+1)-th data line to a fourth subpixel in response to the (j+1)-th gate pulse;

a fifth TFT configured to supply a second data voltage of the first polarity and the first color from a (k+2)-th data line to a fifth subpixel in response to the j-th gate pulse;

a sixth TFT configured to supply a second data voltage of the first polarity and the second color from the (k+2)-th data line to a sixth subpixel in response to the (j+1)-th gate pulse;

a seventh TFT configured to supply a second data voltage of the second polarity and the third color from a (k+3)-th data line to a seventh subpixel in response to the j-th gate pulse; and

an eighth TFT configured to supply a second data voltage of the second polarity and the fourth color from the (k+3)-th data line to an eighth subpixel in response to the (j+1)-th gate pulse.

14. The display device of claim 13, wherein at least one of the even-numbered horizontal lines of the display panel includes:

a ninth TFT configured to supply a third data voltage of the second polarity and the third color from the k-th data line to a ninth subpixel in response to a (j+2)-th gate pulse from a (j+2)-th gate line;

a tenth TFT configured to supply a third data voltage of the second polarity and the fourth color from the k-th data line to a tenth subpixel in response to a (j+3)-th gate pulse from a (j+3)-th gate line;

an eleventh TFT configured to supply a third data voltage of the first polarity and the first color from the (k+1)-th data line to an eleventh subpixel in response to the (j+2)-th gate pulse;

a twelfth TFT configured to supply a third data voltage of the first polarity and the third color from the (k+1)-th data line to a twelfth subpixel in response to the (j+3)-th gate pulse;

a thirteenth TFT configured to supply a fourth data voltage of the second polarity and third color from the (k+2)-th data line to a thirteenth subpixel in response to the (j+2)-th gate pulse;

a fourteenth TFT configured to supply a fourth data voltage of the second polarity and the fourth color from the (k+2)-th data line to a fourteenth subpixel in response to the (j+3)-th gate pulse;

a fifteenth TFT configured to supply a fourth data voltage of the first polarity and the first color from the (k+3)-th data line to a fifteenth subpixel in response to the (j+2)-th gate pulse; and

a sixteenth TFT configured to supply a fourth data voltage of the first polarity and the second color from the (k+3)-th data line to an sixteenth subpixel in response to the (j+3)-th gate pulse.

15. The display device of claim 12, wherein the data voltage from at least one of the even-numbered data lines is configured to be sequentially charged first to a subpixel on the right of the even-numbered data line and then to a subpixel on the left of the even-numbered data line for the at least one of the horizontal lines of the pixel array.

16. The display device of claim 11, wherein the data driver is configured to output the data voltages of a first polarity to (4i+1)-th and (4i+2)-th data lines through (4i+1)-th and (4i+2)-th output channels, respectively, and to output the data voltages of a second polarity to (4i+3)-th and (4i+4)-th data lines through (4i+3)-th and (4i+4)-th output channels, respectively,

wherein the data voltage from at least one of the data lines is sequentially charged first to a subpixel on the left of the data line and then to a subpixel on the right of the data line for at least one of the horizontal lines of the pixel array, and

wherein the data driver is configured to invert the polarity of the data voltages in a cycle of one horizontal period.

17. The display device of claim 16, wherein at least one of the odd-numbered horizontal lines of the pixel array includes:

a first TFT configured to supply a first data voltage of the first polarity and the first color from a k-th data line to a first subpixel in response to a j-th gate pulse from a j-th gate line, where ‘

j’ and

‘

k’

are each a positive integer;

a second TFT configured to supply a first data voltage of the first polarity and the second color from the k-th data line to a second subpixel in response to a (j+1)-th gate pulse from a (j+1)-th gate line;

a third TFT configured to supply a first data voltage of the first polarity and the third color from a (k+1)-th data line to a third subpixel in response to the j-th gate pulse;

a fourth TFT configured to supply a first data voltage of the first polarity and the fourth color from the (k+1)-th data line to a fourth subpixel in response to the (j+1)-th gate pulse;

a fifth TFT configured to supply a first data voltage of the second polarity and the first color from a (k+2)-th data line to a fifth subpixel in response to the j-th gate pulse;

a sixth TFT configured to supply a first data voltage of the second polarity and the second color from the (k+2)-th data line to a sixth subpixel in response to the (j+1)-th gate pulse;

a seventh TFT configured to supply a first data voltage of the second polarity and the third color from a (k+3)-th data line to a seventh subpixel in response to the j-th gate pulse; and

an eighth TFT configured to supply a first data voltage of the second polarity and the fourth color supplied through the (k+3)-th data line to an eighth subpixel in response to the (j+1)-th gate pulse.

18. The display device of claim 17, wherein at least one of the even-numbered horizontal lines of the pixel array includes:

a ninth TFT configured to supply a second data voltage of the second polarity and the third color from the k-th data line to a ninth subpixel in response to a (j+2)-th gate pulse from a (j+2)-th gate line;

a tenth TFT configured to supply a second data voltage of the second polarity and the fourth color from the k-th data line to a tenth subpixel in response to a (j+3)-th gate pulse from a (j+3)-th gate line;

an eleventh TFT configured to supply a second data voltage of the second polarity and the first color from the (k+1)-th data line to an eleventh subpixel in response to the (j+2)-th gate pulse;

a twelfth TFT configured to supply a second data voltage of the second polarity and the second color from the (k+1)-th data line to a twelfth subpixel in response to the (j+3)-th gate pulse;

a thirteenth TFT configured to supply a second data voltage of the first polarity and the third color from the (k+2)-th data line to a thirteenth subpixel in response to the (j+2)-th gate pulse;

a fourteenth TFT configured to supply a second data voltage of the first polarity and the fourth color from the (k+2)-th data line to a fourteenth subpixel in response to the (j+3)-th gate pulse;

a fifteenth TFT configured to supply a second data voltage of the first polarity and the first color from the (k+3)-th data line to a fifteenth subpixel in response to the (j+2)-th gate pulse; and

a sixteenth TFT configured to supply a second data voltage of the first polarity and the second color from the (k+3)-th data line to a sixteenth subpixel in response to the (j+3)-th gate pulse.

19. The display device of claim 11, wherein the data driver is configured to output the data voltages of a first polarity to (8i+1)-th, (8i+3)-th, (8i+6)-th, and (8i+8)-th data lines through (8i+1)-th, (8i+3)-th, (8i+6)-th, and (8i+8)-th output channels, respectively, and to output the data voltages of a second polarity to (8i+2)-th, (8i+4)-th, (8i+5)-th, and (8i+7)-th data lines through (8i+2)-th, (8i+4)-th, (8i+5)-th, and (8i+7)-th output channels, respectively,

wherein the data voltage from at least one of the (8i+1)-th, (8i+4)-th, (8i+6)-th, and (8i+7)-th data lines is configured to be sequentially charged first to a subpixel on the left of the data line and then to a subpixel on the right of the data line for at least one of the horizontal lines of the pixel array,

wherein the data voltage from at least one of the (8i+2)-th, (8i+3)-th, (8i+5)-th, and (8i+8)-th data lines is configured to be sequentially charged first to a subpixel on the right of the even-numbered data line and then to a subpixel on the left of the even-numbered data line for the at least one of the horizontal lines of the pixel array;

and

wherein the data driver is configured to invert the polarity of the data voltages in a cycle of one horizontal period.

20. The display device of claim 19, wherein at least one of the odd-numbered horizontal lines of the pixel array includes:

a first TFT configured to supply a first data voltage of the first polarity and the first color from a k-th data line to a first subpixel in response to a j-th gate pulse from a j-th gate line, where ‘

j’ and

‘

k’

are each a positive integer;

a second TFT configured to supply a first data voltage of the first polarity and the second color from the k-th data line to a second subpixel in response to a (j+1)-th gate pulse from a (j+1)-th gate line;

a third TFT configured to supply a first data voltage of the second polarity and the third color from a (k+1)-th data line to a third subpixel in response to the j-th gate pulse;

a fourth TFT configured to supply a first data voltage of the second polarity and the fourth color from the (k+1)-th data line to a fourth subpixel in response to the (j+1)-th gate pulse;

a fifth TFT configured to supply a second data voltage of the first polarity and the first color from a (k+2)-th data line to a fifth subpixel in response to the j-th gate pulse;

a sixth TFT configured to supply a second data voltage of the first polarity and the second color from the (k+2)-th data line to a sixth subpixel in response to the (j+1)-th gate pulse;

a seventh TFT configured to supply a second data voltage of the second polarity and the third color from a (k+3)-th data line to a seventh subpixel in response to the j-th gate pulse; and

an eighth TFT configured to supply a second data voltage of the second polarity and the fourth color from the (k+3)-th data line to an eighth subpixel in response to the (j+1)-th gate pulse.

21. The display device of claim 20, wherein at least one of the even-numbered horizontal lines of the display panel includes:

a ninth TFT configured to supply a third data voltage of the second polarity and the third color from the k-th data line to a ninth subpixel in response to a (j+2)-th gate pulse from a (j+2)-th gate line;

a tenth TFT configured to supply a third data voltage of the second polarity and the fourth color from the k-th data line to a tenth subpixel in response to a (j+3)-th gate pulse from a (j+3)-th gate line;

an eleventh TFT configured to supply a third data voltage of the first polarity and the first color from the (k+1)-th data line to an eleventh subpixel in response to the (j+2)-th gate pulse;

a twelfth TFT configured to supply a third data voltage of the first polarity and the third color from the (k+1)-th data line to a twelfth subpixel in response to the (j+3)-th gate pulse;

a thirteenth TFT configured to supply a fourth data voltage of the second polarity and third color from the (k+2)-th data line to a thirteenth subpixel in response to the (j+2)-th gate pulse;

a fourteenth TFT configured to supply a fourth data voltage of the second polarity and the fourth color from the (k+2)-th data line to a fourteenth subpixel in response to the (j+3)-th gate pulse;

a fifteenth TFT configured to supply a fourth data voltage of the first polarity and the first color from the (k+3)-th data line to a fifteenth subpixel in response to the (j+2)-th gate pulse; and

a sixteenth TFT configured to supply a fourth data voltage of the first polarity and the second color from the (k+3)-th data line to an sixteenth subpixel in response to the (j+3)-th gate pulse.

22. A display device of claim 10, wherein the four subpixels of each of the pixels are disposed in two adjacent horizontal lines of the pixel array, either with three of the four subpixels disposed in one of the two adjacent horizontal lines and the other subpixel in the other of the two adjacent horizontal lines, or with two of the subpixels disposed in each of the two adjacent horizontal lines.

23. A display device comprising:

a display panel including a plurality of data lines and a plurality of gate lines intersecting the data lines, and a pixel array comprising a plurality of pixels arranged in a matrix form, each pixel being divided into a subpixel having a first color, a subpixel having a second color, a subpixel having a third color, and a subpixel having a fourth color;

a data driver configured to supply data voltages to the data lines;

a gate driver configured to sequentially supply a gate pulse to the gate lines; and

a timing controller configured to transmit data of an input image to the data driver and to control the data driver and the gate driver,

wherein the four subpixels of each of the pixels are disposed in two adjacent horizontal lines of the pixel array, either with three of the four subpixels disposed in one of the two adjacent horizontal lines and the other subpixel in the other of the two adjacent horizontal lines, or with two of the subpixels disposed in each of the two adjacent horizontal lines.