Germanium-Containing FinFET and Methods for Forming the Same
First Claim
1. A method comprising:
- forming isolation regions in a semiconductor substrate;
forming a first semiconductor strip between opposite portions of isolation regions;
forming a second semiconductor strip overlying and contacting the first semiconductor strip;
performing a first recessing to recess the isolation regions, wherein a portion of the second semiconductor strip over top surfaces of remaining portions of the isolation regions forms a semiconductor fin;
performing a second recessing to recess the isolation regions to extend the semiconductor fin downwardly, with an inter-diffusion region of the first semiconductor strip and the second semiconductor strip being exposed after the second recessing; and
etching the inter-diffusion region.
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Accused Products
Abstract
A method includes forming isolation regions in a semiconductor substrate, forming a first semiconductor strip between opposite portions of isolation regions, forming a second semiconductor strip overlying and contacting the first semiconductor strip, and performing a first recessing to recess the isolation regions. A portion of the second semiconductor strip over top surfaces of remaining portions of the isolation regions forms a semiconductor fin. A second recessing is performed to recess the isolation regions to extend the semiconductor fin downwardly, with an inter-diffusion region of the first semiconductor strip and the second semiconductor strip being exposed after the second recessing. The inter-diffusion region is then etched.
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Citations
26 Claims
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1. A method comprising:
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forming isolation regions in a semiconductor substrate; forming a first semiconductor strip between opposite portions of isolation regions; forming a second semiconductor strip overlying and contacting the first semiconductor strip; performing a first recessing to recess the isolation regions, wherein a portion of the second semiconductor strip over top surfaces of remaining portions of the isolation regions forms a semiconductor fin; performing a second recessing to recess the isolation regions to extend the semiconductor fin downwardly, with an inter-diffusion region of the first semiconductor strip and the second semiconductor strip being exposed after the second recessing; and etching the inter-diffusion region. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method comprising:
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forming Shallow Trench Isolation (STI) regions in a semiconductor substrate, with a portion of the semiconductor substrate between opposite portions of the STI regions acting as a first semiconductor strip; recessing a portion of the first semiconductor strip to form a first recess; performing an epitaxy to grow a second semiconductor strip in the recess, wherein the second semiconductor strip contacts the first semiconductor strip; performing a first recessing to recess the STI regions, wherein a portion of the second semiconductor strip is over top surfaces of the recessed STI regions, and forms a semiconductor fin; forming a dummy gate stack to cover a middle portion of the semiconductor fin; forming source and drain regions on opposite sides of the middle portion of the semiconductor fin; forming an Inter-Layer Dielectric (ILD) to cover the source and drain regions; removing the dummy gate stack to form a second recess, wherein the middle portion of the semiconductor fin is exposed to the second recess; performing a second recessing to recess the STI regions; etching an inter-diffusion region of the first semiconductor strip and the second semiconductor strip through the second recess; and forming a gate dielectric and a gate electrode in the second recess, wherein the gate dielectric and the gate electrode are over the middle portion of the semiconductor fin. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15-20. -20. (canceled)
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21. A method comprising:
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forming a first semiconductor strip between opposite portions of Shallow Trench Isolation (STI) regions; forming a second semiconductor strip overlapping and contacting the first semiconductor strip, with edges of the second semiconductor strip aligned to respective edges of the first semiconductor strip; etching an inter-diffusion region of the first semiconductor strip and the second semiconductor strip, wherein an interface region of the first semiconductor strip and the second semiconductor strip is thinned to be narrower than an underlying portion of the first semiconductor strip and an overlying portion of the second semiconductor strip; forming a gate dielectric extending on sidewalls of the first semiconductor strip and the second semiconductor strip; and forming a gate electrode over the gate dielectric. - View Dependent Claims (22, 23, 24, 25, 26)
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Specification