METHODS OF MANUFACTURING NITRIDE SEMICONDUCTOR DEVICES

• US 20150187599A1
• Filed: 06/20/2014
• Published: 07/02/2015
• Est. Priority Date: 12/30/2013
• Status: Active Grant

• Current Assignee: Electronics and Telecommunications Research Institute
• Original Assignee: Electronics and Telecommunications Research Institute
• Inventors: KO, Sang Choon, MUN, Jae Kyoung, CHANG, Woojin, BAE, Sung-Bum, PARK, Young Rak, JUN, Chi Hoon, MOON, Seok-Hwan, NAM, Eun Soo, JANG, Woo-Young, KIM, Jeong-Jin, JANG, Hyungyu, NA, Je Ho
• Granted Patent: US 9,159,583 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/283 Deposition of conductive or insulating materials for electrodes conducting electric current
• CPC Class Codes: H01L 21/28575 on semiconductor bodies comprising AIIIBV compounds
• CPC Class Codes: H01L 21/28581 Deposition of Schottky electrodes
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/452 on AIII-BV compounds
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/7786 with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT

Abstract

Provided is a method of manufacturing a nitride semiconductor device. The method includes forming a plurality of electrodes on a growth substrate on which first and second nitride semiconductor layers are sequentially stacked, forming upper metal layers on the plurality of electrodes respectively, removing the growth substrate to expose a lower surface of the first nitride semiconductor layer, and forming a third nitride semiconductor layer and a lower metal layer sequentially on the exposed lower surface of the first nitride semiconductor layer.

Claims

1. A method of manufacturing a nitride semiconductor device, the method comprising:

forming a plurality of electrodes on a growth substrate on which first and second nitride semiconductor layers are sequentially stacked;

forming upper metal layers on the plurality of electrodes respectively;

removing the growth substrate to expose a lower surface of the first nitride semiconductor layer; and

forming a third nitride semiconductor layer and a lower metal layer sequentially on the exposed lower surface of the first nitride semiconductor layer.

2. The method of claim 1, prior to formation of the plurality of electrodes, further comprising forming an active region by etching the first and second nitride semiconductor layers.

3. The method of claim 2, prior to formation of the plurality of electrodes, further comprising recessing a part of the second nitride semiconductor layer of the active region.

4. The method of claim 3, wherein

the plurality of electrodes comprise first to third electrodes,

the first and second electrodes are formed on the recessed active region, and

the third electrode are formed on the active region between the first and second electrodes.

5. The method of claim 4, wherein the first and second electrodes ohmic-contact with the second nitride semiconductor layer.

6. The method of claim 5, wherein the first and second electrodes comprise a structure in which silicon (Si), titanium (Ti), aluminum (Al), molybdenum (Mo) and gold (Au) are sequentially stacked.

7. The method of claim 1, wherein the third nitride semiconductor layer comprises a material of which a bandgap is wider than that of a material of the first nitride semiconductor layer.

8. The method of claim 7, wherein the third nitride semiconductor layer comprises an aluminum nitride (AlN).

9. The method of claim 1, wherein the removing the growth substrate comprises:

thinning the growth substrate by performing lapping or chemical mechanical polishing (CMP); and

dry-etching a lower surface of the thinned growth substrate.

10. The method of claim 1, prior to removal of the growth substrate, further comprising:

forming an insulating layer over the growth substrate; and

forming a supporting substrate on the insulating layer.

11. The method of claim 10, wherein the insulating layer comprises poly methyl methacrylate (PMMA), and the supporting substrate is bonded to the insulating layer by an adhesive disposed therebetween.

12. The method of claim 1, wherein the forming the lower metal layers comprises sequentially stacking first to third sub metal layers, and wherein the first to third sub metal layers comprise a layered structure of titanium (Ti)/platinum (Pt)/gold (Au), titanium (Ti)/nickel (Ni)/gold (Au) or titanium (Ti)/nickel (Ni)/silver (Ag).

13. The method of claim 1, further comprising forming electrode pads on the upper metal layers.

14. The method of claim 1, further comprising forming a fourth nitride semiconductor layer on the second nitride semiconductor layer.

15. The method of claim 1, wherein the first and second nitride semiconductor layers form a heterostructure.