BALANCING ASYMMETRIC SPACERS

• US 20150187660A1
• Filed: 12/30/2013
• Published: 07/02/2015
• Est. Priority Date: 12/30/2013
• Status: Active Grant

• Current Assignee: Alsephina Innovations Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.))
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Patzer, Joachim, Baars, Peter, Haussdoerfer, Bastian
• Granted Patent: US 9,177,871 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/2652 Through-implantation
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 29/0688 characterised by the particular shape of a junction between semiconductor regions
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

An issue arises when manufacturing semiconductor circuits including PFETs with an SiGe alloy embedded in their source/drain regions and NFETs without any embedded SiGe alloy. In this case, the thickness of the NFET spacers is considerably greater than that of the PFET spacers. In order to alleviate this asymmetry in spacer thickness, a manufacturing flow is proposed wherein a spacer-reducing etching process is introduced before the salicidation. The etching process is performed directly after the ion implantation performed in order to form deep regions of source/drain regions of the NFETs. Thus, the spacer-reducing etching process may be performed in the presence of the same mask used during the NFET deep implantations. The spacer-reducing etching process results in thinning of the NFET spacer structures, thus alleviating the spacer thickness imbalance between NFETs and PFETs.

Claims

1. A method of forming an integrated circuit, comprising:

forming at least a first FET comprising a first gate structure and a first spacer structure formed on the sidewall of said first gate structure;

forming at least a second FET comprising a second gate structure and a second spacer structure formed on the sidewall of said second gate structure, a semiconductor alloy being embedded in the source and/or drain regions of said second FET;

forming a mask layer on said integrated circuit so as to cover said second FET and leave said first FET exposed; and

performing an etching process in the presence of said mask layer so as to decrease the thickness of said first spacer structure.

2. The method of claim 1, wherein said first FET and said second FET have opposite polarities.

3. The method of claim 1, wherein said first FET is an N-channel FET and said second FET is a P-channel FET.

4. The method of claim 1, further comprising performing an ion implantation in the presence of said mask layer before performing said etching process.

5. The method of claim 1, wherein said mask layer comprises a photoresist.

6. The method of claim 1, further comprising removing said mask layer after performing said etching process.

7. The method of claim 6, further comprising performing a silicidation process after removing said mask layer, so as to form a metal silicide layer on predetermined surface portions of said integrated circuit.

8. The method of claim 1, wherein said integrated circuit is formed partly in and partly on a semiconductor layer.

9. The method of claim 1, wherein said embedded semiconductor alloy comprises a portion extending above the surface of said semiconductor layer.

10. The method of claim 1, wherein said portion of said embedded semiconductor alloy protrudes by 10 nm or more from said surface of said semiconductor layer.

11. The method of claim 1, wherein said embedded semiconductor alloy comprises SiGe.

12. The method of claim 1, wherein the concentration of Ge in said embedded semiconductor alloy varies depending on the position.

13. The method of claim 1, wherein said etching process comprises a dry etching process.

14. The method of claim 1, wherein said etching process does not affect said second FET.

15. The method of claim 1, further comprising:

forming an inner portion of said first spacer structure and an inner portion of said second spacer structure next to said first gate structure and said second gate structure, respectively; and

forming an outer portion of said first spacer structure and an outer portion of said second spacer structure above said inner portion of said first spacer structure and said inner portion of said second spacer structure, respectively.

16. The method of claim 15, wherein said mask layer is formed after forming said outer portion of said first spacer structure and said outer portion of said second spacer structure.

17. The method of claim 15, further comprising performing at least one ion implantation after forming said inner portions of said first spacer structure and said second spacer structure and before forming said outer portions of said first spacer structure and said second spacer structure.

18. The method of claim 1, wherein said first gate structure and said second gate structure are formed according to the HKMG technology.

19. The method of claim 1, wherein at least one of said first gate structure and said second gate structure comprises SiON and polysilicon.