FIN CONTACTED ELECTROSTATIC DISCHARGE (ESD) DEVICES WITH IMPROVED HEAT DISTRIBUTION

• US 20150187753A1
• Filed: 01/02/2014
• Published: 07/02/2015
• Est. Priority Date: 01/02/2014
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: GAUTHIER, Robert J. Jr., MITRA, Souvick, MUHAMMAD, Mujahid, CAMPI, John B. Jr., MISHRA, Rahul
• Granted Patent: US 9,236,374 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 27/0262 including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Fin contacted electrostatic discharge (ESD) devices with improved heat distribution and methods of manufacture are disclosed. The method includes forming a plurality of fins on a substrate which is aligned with at least one well region in the substrate. The method further includes forming at least one electrostatic discharge (ESD) device spanning two or more of the plurality of fins. The forming of the ESD device includes forming an epitaxial material spanning the two or more of the plurality of fins and forming one or more contacts on the epitaxial material.

Claims

1. A method comprising:

forming a plurality of fins on a substrate which is aligned with at least one well region in the substrate; and

forming at least one electrostatic discharge (ESD) device spanning two or more of the plurality of fins, wherein the forming of the ESD device comprises;

forming an epitaxial material spanning the two or more of the plurality of fins; and

forming one or more contacts on the epitaxial material.

2. The method of claim 1, further comprising forming a device bounded by shallow trench isolation (STI) structures in the substrate, in FinFET technology.

3. The method of claim 2, wherein the STI bounded device is formed with a buried channel which increases an Si volume in FinFET technology.

4. The method of claim 3, wherein the STI bounded device with the buried channel provides improved heat dissipation in FinFET technology.

5. The method of claim 1, wherein the at least one well region is two well regions comprising forming an N-well region abutting against a P-well region.

6. The method of claim 5, wherein:

the plurality of fins are formed as P+ fins and N+ fins formed in the N-well region and the P-well region; and

the at least one ESD device spans between at least a pair of the P+ fins in the N-well region and the P-well region and at least a pair of the N+ fins in the N-well region and the P-well region.

7. The method of claim 5, further comprising forming a gate structure adjacent to the at least one ESD device, the gate structure spanning the plurality of fins.

8. The method of claim 7, further comprising forming shallow trench isolation structures in the substrate separating each of the plurality of fins.

9. The method of claim 1, wherein the forming of the epitaxial material is a growth process which grows the epitaxial material into direct contact with the substrate.

10. The method of claim 1, wherein the forming of the epitaxial material is a growth process which grows the epitaxial material above the substrate.

11. The method of claim 1, wherein the at least one well region is an N-well region and the plurality of fins are formed as P+ fins and N+ fins on the N-well region.

12. The method of claim 11, wherein the at least one ESD device spans between at least a pair of the P+ fins on the N-well region and at least two separate pairs of the N+ fins on the N-well region, and further comprising forming a gate structure adjacent to the at least one ESD device, the gate structure spanning the plurality of fins and forming a heat sink to dissipate heat generated from the at least one ESD device to the substrate, wherein the forming the gate structure includes a replacement gate process.

13. The method of claim 12, further comprising forming shallow trench isolation structures within the N-well region and between each of the plurality of fins.

14. A method comprising:

forming at least one well region in a substrate;

forming a plurality of fins over the at least one well region;

forming a plurality of ESD devices spanning sets of the plurality of fins, the forming of the plurality of ESD devices comprises;

growing epitaxial material on the sets of the plurality of fins; and

forming contacts on the epitaxial material;

forming metal gate structures spanning the plurality of fins and separating each of the plurality of ESD devices along lengths of the sets of the plurality of fins; and

forming shallow trench isolation structures within the at least one well region and between each of the plurality of fins.

15. The method of claim 14, wherein the at least one well region is two well regions, including an N-well region abutting against a P-well region.

16. The method of claim 15, wherein:

the plurality of fins are formed as P+ fins and N+ fins formed in the N-well region and the P-well region; and

the plurality of ESD devices span between at least a pair of the P+ fins in the N-well region and the P-well region and at least a pair of the N+ fins in the N-well region and the P-well region.

17. The method of claim 14, wherein the forming of the epitaxial material is a growth process.

18. The method of claim 14, wherein:

the at least one well region is an N-well region and the plurality of fins are P+ fins and N+ fins formed on the N-well region; and

each of the plurality of ESD devices span between at least a pair of the P+ fins on the N-well region and at least two separate pairs of the N+ fins on the N-well region.

19. The method of claim 18, wherein the metal gate structures are adjacent to each of the plurality of ESD devices and act as heat sinks to dissipate heat generated from the ESD devices into the substrate.

20. A structure, comprising:

a substrate;

a well implant in the substrate;

a set of P+ fins on the well;

a set of N+ fins on the well;

a plurality of shallow trench isolation (STI) structures formed in the substrate, separating the N+ fins and the P+ fins; and

at least one electrostatic discharge (ESD) device spanning two or more of the set of P+ fins or set of N+ fins.