Method for Manufacturing a Semiconductor Device and a Semiconductor Device

• US 20150187761A1
• Filed: 12/27/2013
• Published: 07/02/2015
• Est. Priority Date: 12/27/2013
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Irsigler, Peter, Baumgartl, Johannes, Zundel, Markus, Mauder, Anton, Hirler, Franz, Weis, Rolf
• Granted Patent: US 9,449,968 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/2236 from or into a plasma phase
• CPC Class Codes: H01L 21/225 using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer H01L21/221 - H01L21/222 take precedence
• CPC Class Codes: H01L 21/2254 from or through or into an applied layer, e.g. photoresist, nitrides
• CPC Class Codes: H01L 21/2255 the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0865 Disposition
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66696 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66704 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device is formed by forming: a transistor in a semiconductor substrate having a main surface; a source region and a drain region; and a channel region and a drift zone between the source region and the drain region. The source and drain regions are arranged along a first direction parallel to the main surface. Gate trenches and a gate electrode are formed in the gate trenches. The gate trenches have a distance corresponding to a width d1 of the channel region, where d1≦2*ld and ld denotes a length of a depletion zone formed at an interface between the channel region and a gate dielectric adjacent to the gate electrode. An auxiliary trench formed in the main surface extends in a second direction intersecting the first direction. The source region is formed using a doping method that introduces dopants via a sidewall of the auxiliary trench.

Claims

1. A method of forming a semiconductor device comprising forming a transistor in a semiconductor substrate having a main surface, the method further comprising:

forming a source region and a drain region;

forming a channel region and a drift zone arranged between the source region and the drain region, the source region and the drain region being arranged along a first direction parallel to the main surface;

forming gate trenches and a gate electrode in the gate trenches, the gate trenches having a distance corresponding to a width d1 of the channel region, the width d1 fulfilling;

d1≦

2*ld, where ld denotes a length of a depletion zone formed at an interface between the channel region and a gate dielectric adjacent to the gate electrode; and

forming an auxiliary trench in the main surface, the auxiliary trench extending in a second direction intersecting the first direction, the source region being formed using a doping method that introduces dopants via a sidewall of the auxiliary trench.

2. The method according to claim 1, wherein forming the auxiliary trench comprises an anisotropic etching process to form the auxiliary trench having sidewalls that are approximately perpendicular with respect to the main surface.

3. The method according to claim 1, wherein the doping method is selected from the group consisting of ion implantation, plasma assisted doping, doping via CVD glasses, doped selective epitaxial processes, and deposition of p or n doped polysilicon.

4. The method according to claim 1, wherein the doping method comprises depositing a doping layer on a sidewall of the auxiliary trench, the doping layer including the dopant, and performing a diffusion process.

5. The method according to claim 1, wherein forming the auxiliary trench comprises an etching process to form the auxiliary trench having tapered sidewalls.

6. The method according to claim 1, further comprising:

forming a sacrificial material filling the auxiliary trench;

forming first openings in the sacrificial material; and

performing a first doping process to form a body contact region by doping a substrate material adjacent to the first openings.

7. The method according to claim 6, further comprising:

forming second openings in the sacrificial material; and

performing a second doping process to form a source region by doping the substrate material adjacent to the second openings.

8. The method according to claim 1, further comprising:

doping a substrate portion adjacent to a bottom side of the auxiliary trench with dopants of a first conductivity type to form a body contact region; and

doping a substrate portion adjacent to the main surface with dopants of a second conductivity type to form the source region.

9. The method according to claim 1, wherein the auxiliary trench has a depth approximately equal to the depth of the gate trenches.

10. A semiconductor device comprising a transistor in a semiconductor substrate having a main surface, the transistor comprising:

source regions and drain regions, each of the source regions and the drain regions being arranged at the main surface;

channel regions between the source regions and the drain regions;

gate trenches in the main surface, disposed between adjacent ones of the channel regions;

gate electrodes in gate trenches; and

body contact regions at the main surface, the body contact regions contacting the channel regions,

wherein the source regions and the body contact regions are alternatingly disposed along a second direction intersecting the first direction.

11. The semiconductor device according to claim 10, wherein the source regions are doped with dopants of a first conductivity type, and the body contact regions are doped with dopants of a second conductivity type.

12. The semiconductor device according to claim 11, wherein the source regions are electrically connected to the body contact regions.

13. The semiconductor device according to claim 10, wherein the gate trenches comprise first and second gate trenches, the first gate trenches being arranged at the source regions, the second gate trenches being arranged at the body contact regions.

14. The semiconductor device according to claim 13, wherein the first gate trenches are filled with a conductive filling that is electrically connected to a gate terminal.

15. The semiconductor device according to claim 14, wherein the second gate trenches are filled with a conductive filling that is electrically connected to a source terminal.

16. The semiconductor device according to claim 13, wherein the second gate trenches are filled with an insulating material.

17. The semiconductor device according to claim 10, further comprising a drift zone between the channel region and the drain region.

18. The semiconductor device according to claim 10, wherein the first and the second gate trenches extend to approximately the same depth as the source contacts.

19. The semiconductor device according to claim 10, wherein the first and the second gate trenches extend to approximately the same depth as the body contact regions.

20. An integrated circuit comprising the semiconductor device according to claim 10.