THREE-DIMENSIONAL NON-VOLATILE MEMORY

• US 20150187784A1
• Filed: 12/30/2013
• Published: 07/02/2015
• Est. Priority Date: 12/30/2013
• Status: Active Grant

• Current Assignee: Globalfoundries Singapore Pte Limited (GlobalFoundries, Inc.)
• Original Assignee: Globalfoundries Singapore Pte Limited (GlobalFoundries, Inc.)
• Inventors: TAN, Shyue Seng, TOH, Eng Huat, QUEK, Elgin Kiok Boone
• Granted Patent: US 9,171,855 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H01L 29/7889 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

A three-dimensional one-transistor non-volatile memory device and a manufacturing method thereof are provided. The memory device includes a primary fin disposed on a substrate along a first direction, first and second secondary fins disposed on the substrate along a second direction, and a first gate of a first memory cell disposed on the substrate in a gate region thereof. The first gate includes a program gate, a floating gate and a control gate.

Claims

1. A memory device, comprising:

a primary fin disposed on a substrate along a first direction;

first and second secondary fins disposed on the substrate along a second direction; and

a first gate of a first memory cell disposed on the substrate in a gate region thereof, wherein the first gate comprises

a program gate disposed on the substrate, wherein the program gate is displaced from the primary fin by a dielectric block which is disposed on the substrate and adjacent to the primary fin, and wherein the dielectric block has a height which is less than that of the program gate,

a floating gate disposed over the program gate, wherein the program gate is separated from the floating gate and the primary fin by an inter-gate dielectric, and wherein the floating gate comprises a floating gate tip disposed adjacent to the program gate and the dielectric block and between the program gate and the primary fin, and

a control gate disposed adjacent to the floating gate and the program gate, wherein the control gate is separated from the substrate, the program gate, and the floating gate by the inter-gate dielectric.

2. The memory device of claim 1, further comprising a source region and a drain region in the primary fin and disposed on opposing sides of the first gate.

3. The memory device of claim 1, further comprising a first well region in the substrate and in electrical contact with the program gate, wherein during a program operation electrons flow from the program gate to the floating gate through a poly-to-poly tunneling effect.

4. The memory device of claim 1, further comprising an isolation well below the primary fin and the secondary fins to electrically isolate the first memory cell from the substrate.

5. The memory device of claim 1, wherein the primary fin is shared by the first gate of the first memory cell and a second gate of a second memory cell, wherein the first and second gates are disposed on opposing sides of the primary fin, and wherein the first and second memory cells form a column of memory cells.

6. The memory device of claim 1, wherein the first secondary fin forms a bit line for at least the first memory cell.

7. The memory device of claim 1, wherein the second secondary fin forms a source line for at least the first memory cell.

8. The memory device of claim 1, wherein the control gate is coupled to a word line for at least the first memory cell.

9. A method of manufacturing a memory device, comprising:

forming a primary fin on a substrate along a first direction;

forming first and second secondary fins on the substrate along a second direction; and

forming a first gate of a first memory cell on the substrate in a gate region thereof, wherein forming the first gate comprises

forming a program gate on the substrate,

forming a dielectric block on the substrate and adjacent to the primary fin, wherein the program gate is displaced from the primary fin by the dielectric block, and wherein the dielectric block has a height which is less than that of the program gate,

forming a floating gate over the program gate, wherein the floating gate comprises a floating gate tip disposed adjacent to the program gate and the dielectric block and between the program gate and the primary fin,

forming an inter-gate dielectric, wherein the program gate is separated from the floating gate and the primary fin by the inter-gate dielectric, and

forming a control gate adjacent to the floating gate and the program gate, wherein the control gate is separated from the substrate, the program gate, and the floating gate by the inter-gate dielectric.

10. The method of claim 9, further comprising forming a source region and a drain region in the primary fin and disposed on opposing sides of the first gate.

11. The method of claim 9, further comprising forming a first well region in the substrate, wherein the first well is in electrical contact with the program gate, and wherein during a program operation electrons flow from the program gate to the floating gate through a poly-to-poly tunneling effect.

12. The method of claim 9, further comprising forming an isolation well below the primary fin and the secondary fins to electrically isolate the first memory cell from the substrate.

13. The method of claim 9, wherein forming the primary fin comprises forming the primary fin to be shared by the first gate of the first memory cell and a second gate of a second memory cell, wherein the first and second gates are disposed on opposing sides of the primary fin, and wherein the first and second memory cells form a column of memory cells.

14. The method of claim 9, wherein forming the first secondary fin comprises forming the first secondary fin as a bit line for at least the first memory cell.

15. The method of claim 9, wherein forming the second secondary fin comprises forming the second secondary fin as a source line for at least the first memory cell.

16. The method of claim 9, wherein forming the control gate comprises forming the control gate such that the control gate is coupled to a word line for at least the first memory cell.

17. A memory device, comprising:

a substrate having a first primary side and a second primary side opposite the first primary side, the substrate including a well region therein that is doped with dopants of a first electrical polarity, the substrate having one or more fins protruding from the first primary side, a first fin of the one or more fins having a first side and a second side opposite the first side;

a hard mask layer disposed over the first fin of the one or more fins;

a first gate stack formed on the first side of the first fin; and

a second gate stack formed on the second side of the first fin,

wherein the first gate stack comprises a first section of a first polysilicon layer configured to function as a first program gate and disposed over the first primary side of the substrate, a first section of a second polysilicon layer configured to function as a first floating gate and disposed over the first program gate, and a first section of a third polysilicon layer configured to function as a first control gate and disposed over the first floating gate, and

wherein the second gate stack comprises a second section of the first polysilicon layer configured to function as a second program gate and disposed over the first primary side of the substrate, a second section of the second polysilicon layer configured to function as a second floating gate and disposed over the second program gate, and a second section of the third polysilicon layer configured to function as a second control gate and disposed over the second floating gate.

18. The memory device of claim 17, wherein the first floating gate at least partially wraps around a corner of the first program gate that is closest to the hard mask layer when viewed along a longitudinal direction of the first fin.

19. The memory device of claim 17, wherein the first control gate has a generally L-shaped contour when viewed along a longitudinal direction of the first fin such that the first control gate is over and adjacent to the first floating gate and the first program gate.

20. The memory device of claim 17, wherein the substrate comprises a silicon-on-insulator (SOI) substrate.