Low Sheet Resistance GaN Channel on Si Substrates Using InAlN and AlGaN Bi-Layer Capping Stack

• US 20150187924A1
• Filed: 12/26/2013
• Published: 07/02/2015
• Est. Priority Date: 12/26/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Sansaptak Dasgupta
• Inventors: Dasgupta, Sansaptak, Then, Han Wui, Radosavljevic, Marko, Gardner, Sanaz K., Sung, Seung Hoon, Chu-Kung, Benjamin, Chau, Robert S.
• Granted Patent: US 9,660,064 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/30612 Etching of AIIIBV compounds
• CPC Class Codes: H01L 21/30617 Anisotropic liquid etching
• CPC Class Codes: H01L 29/155 Comprising only semiconductor materials H01L29/154 takes precedence
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/7783 using III-V semiconductor material
• CPC Class Codes: H01L 29/7786 with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT

Abstract

Transistors or transistor layers include an InAlN and AlGaN bi-layer capping stack on a 2DEG GaN channel, such as for GaN MOS structures on Si substrates. The GaN channel may be formed in a GaN buffer layer or stack, to compensate for the high crystal structure lattice size and coefficient of thermal expansion mismatch between GaN and Si. The bi-layer capping stack an upper InAlN layer on a lower AlGaN layer to induce charge polarization in the channel, compensate for poor composition uniformity (e.g., of Al), and compensate for rough surface morphology of the bottom surface of the InAlN material. It may lead to a sheet resistance between 250 and 350 ohms/sqr. It may also reduce bowing of the GaN on Si wafers during growth of the layer of InAlN material, and provide a AlGaN setback layer for etching the InAlN layer in the gate region.

Claims

1. A method to form transistor layers comprising:

forming a GaN channel layer of GaN material on a top surface of a substrate;

forming a bi-layer capping stack on a top surface of the GaN channel layer, wherein forming the bi-layer capping stack includes;

forming a lower capping AlGaN layer of AlGaN material on a top surface of an AlN layer formed on the top surface of the GaN channel layer; and

forming an upper capping AlInN layer of AlInN material on a top surface of the AlGaN material.

2. The method of claim 1, wherein the GaN channel layer comprises a GaN stack having a plurality of GaN layers separated by AlN layers, and wherein the bi-layer capping stack causes a sheet resistance of between 200 and 300 ohms per SQR in a 2DEG channel formed in a upper thickness of the GaN layer.

3. The method of claim 1, wherein the AlGaN layer has a thickness of between 2 and 10 nm, and causes an electron density of greater than 2.5 E13 cm/2;

and wherein the AlInN layer has a thickness of between 5 and 15 nm, and causes a channel mobility of between 900 and 1000 CM2.

4. The method of claim 1, wherein the AlGaN layer comprises Al_XGa_(1-X)N, where X is less than 0.4;

and

wherein the AlInN layer is Al_YIn_(1-Y)N, where Y is greater than 0.8.

5. The method of claim 1, wherein a top surface of the AlGaN material forms a setback material surface upon which the AlInN material may be selectively etched.

6. The method of claim 1, further comprising:

forming a gate over a top surface of the AlGaN layer; and

forming junction regions on the AlInN layer on either side of the gate.

7. The method of claim 6, wherein forming the gate comprises:

selectively etching the AlInN material to expose a top surface of the AlGaN material, wherein selectively etching the AlInN material comprises using a wet etch including a KOH or a NH4OH solution to selectively etch the AlInN material but not etch the AlGaN material;

forming a gate dielectric over the exposed surface of the AlGaN material; and

forming a metal gate electrode on the gate dielectric.

8. The method of claim 1, wherein the AlGaN layer has a predetermined thickness configured to cause electrons in a 2DEG channel of the GaN material of the GaN channel layer to be subject to less interface roughness scattering and less alloy scattering, and thus provide a higher mobility than without the AlGaN layer.

9. The method of claim 1, wherein forming the GaN channel layer comprises forming the GaN material in a chamber at a temperature of approximately 1050 degrees Celsius (C);

wherein forming the AlGaN layer comprises forming AlGaN in a chamber at a temperature of between 1000 and 1050 degrees C; and

wherein forming the AlInN layer comprises forming AlInN material in a chamber at a temperature between 700 and 750 degrees C.

10. The method of claim 1, wherein the transistor is part of one of a voltage regulator, a power management integrated circuit (IC), a radio frequency (RF) power amplifier, or a system on a chip (SoC).

25. The method of claim 1, wherein the AlGaN material is formed on and touching a top surface of AlN material of the AlN layer, and wherein the AlInN material is formed on and touching a top surface of the AlGaN material.

11. Transistor layers comprising:

a GaN channel layer of GaN material on a top surface of a substrate;

a bi-layer capping stack on a top surface of the GaN channel layer, wherein the bi-layer capping stack includes;

a lower capping AlGaN layer of AlGaN material on a top surface of an AlN layer on the top surface of the GaN channel layer; and

an upper capping AlInN layer of AlInN material on a top surface of the AlGaN material.

12. The transistor of claim 11, wherein the GaN channel layer comprises a GaN stack having a plurality of GaN layers separated by AlN layers, and wherein the bi-layer capping stack causes a sheet resistance of between 200 and 300 ohms per SQR in a 2DEG channel formed in a upper thickness of the GaN layer.

13. The transistor of claim 11, wherein the AlGaN layer has a thickness of between 2 and 10 nm, and causes an electron density of greater than 2.5 E13 cm/2;

and wherein the AlInN layer has a thickness of between 5 and 30 nm, and causes a channel mobility of between 900 and 1400 CM2/V−

s.

14. The transistor of claim 11, wherein the AlGaN layer comprises Al_XGa_(1-X)N, where X is less than 0.4;

and

wherein the AlInN layer is Al_YIn_(1-Y)N, where Y is greater than 0.8.

15. The transistor of claim 11, wherein a top surface of the AlGaN material forms a setback material surface upon which the AlInN material may be selectively etched.

16. The transistor of claim 11, further comprising:

a gate over a top surface of the AlGaN layer; and

junction regions on the AlInN layer on either side of the gate.

17. The transistor of claim 16, wherein the gate comprises:

a gate dielectric over an exposed surface of the AlGaN material in a trench; and

a metal gate electrode on the gate dielectric in the trench.

18. The transistor of claim 11, wherein the AlGaN layer has a predetermined thickness configured to cause electrons in a 2DEG channel of the GaN material of the GaN channel layer to be subject to less interface roughness scattering and less alloy scattering, and thus provide a higher mobility than without the AlGaN layer.

19. The transistor of claim 11, wherein the transistor is part of one of a voltage regulator, a power management integrated circuit (IC), a radio frequency (RF) power amplifier, or a system on a chip (SoC).

26. The transistor of claim 11, wherein the AlGaN material is formed on and touching a top surface of AlN material of the AlN layer, and wherein the AlInN material is formed on and touching a top surface of the AlGaN material.

20. A system for computing comprising:

a microprocessor coupled to a memory, the microprocessor having at least one electronic transistor having transistor layers comprising;

a GaN channel layer of GaN material on a top surface of a substrate;

a bi-layer capping stack on a top surface of the GaN channel layer, wherein the bi-layer capping stack includes;

a lower capping AlGaN layer of AlGaN material on a top surface of an AlN layer on the top surface of the GaN channel layer; and

an upper capping AlInN layer of AlInN material on a top surface of the AlGaN material.

21. The system of claim 20, wherein the AlGaN layer has a thickness of between 2 and 10 nm, and causes an electron density of greater than 2.5 E13 cm/2;

and wherein the AlInN layer has a thickness of between 5 and 15 nm, and causes a channel mobility of between 900 and 1400 CM2/V−

s, and wherein the bi-layer capping stack causes a sheet resistance of between 200 and 300 ohms per SQR in a 2DEG channel formed in a upper thickness of the GaN channel layer.

22. The system of claim 20, wherein the AlGaN layer comprises Al_XGa_(1-X)N, where X is less than 0.4;

and

wherein the AlInN layer is Al_YIn_(1-Y)N, where Y is greater than 0.8.

23. The system of claim 20, further comprising:

a gate over a top surface of the AlGaN layer, wherein the gate comprises;

a gate dielectric over an exposed surface of the AlGaN material in a trench; and

a metal gate electrode on the gate dielectric in the trench; and

junction regions on the AlInN layer on either side of the gate.

24. The system of claim 20, wherein the transistor is part of one of a voltage regulator, a power management integrated circuit (IC), a radio frequency (RF) power amplifier, or a system on a chip (SoC).

27. The system of claim 20, wherein the AlGaN material is formed on and touching a top surface of AlN material of the AlN layer, and wherein the AlInN material is formed on and touching a top surface of the AlGaN material.