Metal Gate Transistor and Method for Tuning Metal Gate Profile

• US 20150187939A1
• Filed: 12/31/2013
• Published: 07/02/2015
• Est. Priority Date: 12/31/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wu, Po-Chi, Fang, Buh-Kuan, Chang, Yung-Jung, Leu, Po-Hsiung
• Granted Patent: US 9,356,120 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/3105 After-treatment
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers

Abstract

A semiconductor device having arrays of metal gate transistors is fabricated by forming a number of dummy gate structures including a first gate dielectric layer and a dummy gate material layer overlying the first gate dielectric layer, depositing a tensile ILD layer between the dummy gate structures, stressing the tensile ILD layer, removing at least the dummy gate material to form a number of trenches, and depositing a metal gate material in the trenches, which have a tapered profile.

Claims

1. A method of fabricating a semiconductor device, comprising:

forming a plurality of dummy gate structures including a first gate dielectric layer and a dummy gate material layer overlying the first gate dielectric layer;

depositing a tensile ILD layer between the plurality of dummy gate structures;

stressing the tensile ILD layer;

removing at least the dummy gate material from the plurality of dummy gate structures to form a plurality of trenches; and

depositing a metal gate material in the plurality of trenches;

wherein the plurality of trenches each has a tapered profile.

2. The method of claim 1, wherein stressing the tensile ILD layer comprises at least one of annealing, chemical treating, and exposing to UV radiation.

3. The method of claim 2, wherein the stressing the tensile ILD layer is performed after removing at least the dummy gate material.

4. The method of claim 1, wherein the depositing a tensile ILD layer is exposing an area between the plurality of dummy gate structures to a siloxane precursor in a high aspect ratio process (HARP).

5. The method of claim 4, wherein the depositing a tensile ILD layer also includes exposing the siloxane precursor to a remote plasma.

6. The method of claim 4, wherein the siloxane precursor is an alkoxysilane precursor.

7. The method of claim 1, wherein the at least the dummy gate material includes the first gate dielectric and the method further comprises depositing a second gate dielectric.

8. The method of claim 7, wherein the second gate dielectric comprises HfO₂, TiO₂, HfZrO, Ta₂O₃, HfSiO₄, ZrO₂, or ZrSiO₂.

9. The method of claim 1, wherein the first gate dielectric layer is a high k dielectric layer, wherein the dielectric constant, k, is greater than or equal to about 4.0.

10. The method of claim 1, wherein the depositing a metal gate material comprises depositing a work function metal and a fill metal.

11. The method of claim 1, wherein the tensile ILD layer has a tensile stress of about 200 MPa to about 1400 MPa after the stressing operation.

12. The method of claim 1, wherein the dummy gate material layer is polysilicon.

13. A device, comprising:

a plurality of metal gate structures including a high-k gate dielectric layer and a metal layer, wherein the metal layer has a top width larger than a bottom width; and

a tensile inter-level dielectric (ILD) layer between the plurality of metal gate structures.

14. The device of claim 13, wherein a difference in width between the top width and the bottom width is less than about 3 nm.

15. The device of claim 13, wherein the metal layer has a top width to bottom width ratio of about 1.2.

16. The device of claim 13, wherein a cross section of the metal layer is a pseudo-trapezoid with curved sides.

17. The device of claim 13, wherein the metal layer is one of TiN, TaN, Ru, Mo, Al, WN, ZrSi₂, MoSi₂, TaSi₂, NiSi₂, or WN.

18. The device of claim 13, wherein the metal layer is one of Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, or Zr.

19. The device of claim 13, wherein the tensile ILD is a tensile silicon oxide formed from an alkoxysilane precursor.

20. The device of claim 19, wherein the tensile silicon oxide includes carbon.