APPARATUS FOR SYMMETRIC AND LINEAR TIME-TO-DIGITAL CONVERTER (TDC)
First Claim
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1. An apparatus comprising:
- a first input;
a second input;
a first delay line having a plurality of delay stages coupled together in series, the first delay line to receive the first input;
a second delay line having a plurality of delay stages coupled together in series, the second delay line to receive the second input; and
a plurality of comparators, each having first and second inputs coupled to the first and second delay lines,wherein multiple delay stages of the first and second delay lines are coupled to provide equally delayed input signals for two comparators.
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Abstract
Described is a linear and symmetric time-to-digital converter (TDC) which comprises: a first input; a second input; a first delay line having a plurality of delay stages coupled together in series, the first delay line to receive the first input; a second delay line having a plurality of delay stages coupled together in series, the second delay line to receive the second input; and a plurality of comparators, each having first and second outputs coupled to the first and second delay lines.
40 Citations
20 Claims
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1. An apparatus comprising:
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a first input; a second input; a first delay line having a plurality of delay stages coupled together in series, the first delay line to receive the first input; a second delay line having a plurality of delay stages coupled together in series, the second delay line to receive the second input; and a plurality of comparators, each having first and second inputs coupled to the first and second delay lines, wherein multiple delay stages of the first and second delay lines are coupled to provide equally delayed input signals for two comparators. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A phase locked loop (PLL) comprising:
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an oscillator to generate an output clock; a divider to receive the output clock and to generate a feedback clock; a time-to-digital converter (TDC) for comparing a reference clock with the feedback clock, the TDC including; a first input; a second input; a first delay line having a plurality of delay stages coupled together in series, the first delay line to receive the first input; a second delay line having a plurality of delay stages coupled together in series, the second delay line to receive the second input; and a plurality of comparators, each having first and second inputs coupled to the first and second delay lines, wherein multiple delay stages of the first and second delay lines are coupled to provide equally delayed input signals for two comparators; and a controller to receive output of the TDC and to generate a code indicating direction of change in frequency of the output clock. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17)
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18. A system comprising:
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a memory; a processor coupled to the memory, the processor having a time-to-digital converter comprising; a first input; a second input; a first delay line having a plurality of delay stages coupled together in series, the first delay line to receive the first input; a second delay line having a plurality of delay stages coupled together in series, the second delay line to receive the second input; and a plurality of comparators, each having first and second inputs coupled to the first and second delay lines, wherein multiple delay stages of the first and second delay lines are coupled to provide equally delayed input signals for two comparators; and a wireless interface for allowing the processor to communicate with another device. - View Dependent Claims (19, 20)
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Specification