ADAPTIVE ADMISSION CONTROL FOR ON DIE INTERCONNECT

• US 20150188797A1
• Filed: 12/27/2013
• Published: 07/02/2015
• Est. Priority Date: 12/27/2013
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Satat, Guy, Bolotin, Evgeny, Mandelblat, Julius, Gaur, Jayesh, Majumder, Supratik, Venkatesan, Ravi K.
• Application Number:
  US14/142,748
• Publication Number:
  US 20150188797A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 15/17337 Direct connection machines, e.g. completely connected computers, point to point communication networks coupling between buses G06F13/4004
• CPC Class Codes: G06F 15/7825 Globally asynchronous, locally synchronous, e.g. network on chip
• CPC Class Codes: H04L 43/0817 by checking functioning
• CPC Class Codes: H04L 43/16 Threshold monitoring
• CPC Class Codes: H04L 47/12 Avoiding congestion; Recovering from congestion
• CPC Class Codes: H04L 47/25 with rate being modified by the source upon detecting a change of network conditions

Abstract

Methods and apparatus relating to adaptive admission control for on die interconnect are described. In one embodiment, admission control logic determines whether to cause a change in an admission rate of requests from one or more sources of data based at least in part on comparison of a threshold value and resource utilization information. The resource utilization information is received from a plurality of resources that are shared amongst the one or more sources of data. The threshold value is determined based at least in part on a number of the plurality of resources that are determined to be in a congested condition. Other embodiments are also disclosed.

Claims

1. An apparatus comprising:

logic to determine whether to cause a change in an admission rate of requests from one or more sources of data based at least in part on comparison of a threshold value and resource utilization information,

wherein the resource utilization information is to be received from a plurality of resources that are shared amongst the one or more sources of data, wherein the one or more sources of data are coupled to communicate via an interconnect, and wherein the threshold value is to be determined based at least in part on a number of the plurality of resources that are determined to be in a congested condition.

2. The apparatus of claim 1, wherein each of the one or more sources of data is to communicate with the interconnect via a network interface and wherein the logic is to cause a change in the admission rate of requests from the one or more sources of data via a corresponding network interface.

3. The apparatus of claim 1, wherein the one or more sources of data are to comprise one or more of:

a general purpose processor core and a graphics processor core.

4. The apparatus of claim 1, wherein the plurality of resources are to comprise one or more of:

one or more caches and a memory controller.

5. The apparatus of claim 4, wherein the one or more caches are to communicate their utilization value to the logic in series.

6. The apparatus of claim 1, comprising logic to monitor the plurality of resources to determine the resource utilization information.

7. The apparatus of claim 1, wherein the logic is to cause the change in the admission rate of requests from the one or more sources of data based at least in part on admission control policy transmission.

8. The apparatus of claim 1, wherein the logic is to couple a first agent to a second agent.

9. The apparatus of claim 8, wherein one or more of the first agent and the second agent are to comprise a plurality of processor cores.

10. The apparatus of claim 8, wherein one or more of the first agent and the second agent are to comprise a plurality of sockets.

11. The apparatus of claim 1, wherein the interconnect is to comprise a ring interconnect.

12. The apparatus of claim 1, wherein the interconnect is to comprise a point-to-point interconnect.

13. The apparatus of claim 1, wherein one or more of:

the logic, one or more general purpose processor cores, one or more graphics processor cores, a memory controller, and memory are on a same integrated circuit die.

14. A method comprising:

determining whether to cause a change in an admission rate of requests from one or more sources of data based at least in part on comparison of a threshold value and resource utilization information,

wherein the resource utilization information is received from a plurality of resources that are shared amongst the one or more sources of data, wherein the one or more sources of data communicate via an interconnect, and wherein the threshold value is determined based at least in part on a number of the plurality of resources that are determined to be in a congested condition.

15. The method of claim 14, further comprising each of the one or more sources of data communicating with the interconnect via a network interface and causing a change in the admission rate of requests from the one or more sources of data via a corresponding network interface.

16. The method of claim 14, further comprising the one or more caches communicating their utilization value in series.

17. The method of claim 14, further comprising monitoring the plurality of resources to determine the resource utilization information.

18. The method of claim 14, further comprising causing the change in the admission rate of requests from the one or more sources of data based at least in part on admission control policy transmission.

19. The method of claim 14, wherein the interconnect is to comprise a ring interconnect.

20. The method of claim 14, wherein the interconnect is to comprise a point-to-point interconnect.

21. A system comprising:

memory to store resource utilization information; and

logic to determine whether to cause a change in an admission rate of requests from one or more sources of data based at least in part on comparison of a threshold value and the resource utilization information,

wherein the resource utilization information is to be received from a plurality of resources that are shared amongst the one or more sources of data, wherein the one or more sources of data are coupled to communicate via an interconnect, and wherein the threshold value is to be determined based at least in part on a number of the plurality of resources that are determined to be in a congested condition.

22. The system of claim 21, wherein each of the one or more sources of data is to communicate with the interconnect via a network interface and wherein the logic is to cause a change in the admission rate of requests from the one or more sources of data via a corresponding network interface.

23. The system of claim 21, wherein the one or more sources of data are to comprise one or more of:

a general purpose processor core and a graphics processor core.

24. The system of claim 21, wherein the plurality of resources are to comprise one or more of:

one or more caches and a memory controller.

25. The system of claim 21, comprising logic to monitor the plurality of resources to determine the resource utilization information.