Use of a (Digital) PUF for Implementing Physical Degradation/Tamper Recognition for a Digital IC

• US 20150192637A1
• Filed: 06/05/2013
• Published: 07/09/2015
• Est. Priority Date: 07/17/2012
• Status: Abandoned Application

• Current Assignee: Siemens AG
• Original Assignee: Siemens AG
• Inventors: Falk, Rainer, Mucha, Andreas
• Application Number:
  US14/415,369
• Publication Number:
  US 20150192637A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G01R 31/2855 Environmental, reliability or burn-in testing
• CPC Class Codes: G06F 21/55 Detecting local intrusion or implementing counter-measures
• CPC Class Codes: G06F 21/86 Secure or tamper-resistant housings
• CPC Class Codes: H03K 19/003 Modifications for increasing the reliability for protection
• CPC Class Codes: H04L 2209/12 Details relating to cryptographic hardware or logic circuitry
• CPC Class Codes: H04L 9/3278 using physically unclonable functions [PUF]

Abstract

An integrated circuit configured for malfunction detection includes an integrity sensor and a test unit. The integrity sensor is based on a physical, unclonable function. The test unit is configured to send a challenge signal to the integrity sensor, and to determine information about a degradation of the integrated circuit. The information is based on a response signal subsequently generated by the physical, unclonable function and sent by the integrity sensor to the test unit.

Claims

1. An integrated circuit, comprising:

an integrity sensor; and

a checking unit;

wherein the integrity sensor is based on a physical, unclonable function, wherein the integrity sensor is configured to receive a challenge signal and to use the challenge signal to send a response signal to the checking unit, and wherein the response signal is produced using the physical unclonable function; and

wherein the checking unit is configured to receive the response signal and to use the response signal to determine first information about degradation of the integrated circuit.

2. The integrated circuit of claim 1, wherein the checking unit is further configured to use the first information to determine additional information about the degradation of the integrated circuit caused by aging processes.

3. The integrated circuit of claim 1, wherein the checking unit is further configured to use the first information about the degradation to determine physical damage to the integrated circuit or manipulation of the integrated circuit.

4. The integrated circuit of claim 1, wherein the checking unit is further configured to determine whether degradation of the integrated circuit is attributable to physical manipulation or an aging process.

5. The integrated circuit of claim 1, wherein the checking unit is further configured to use a time profile of the first information about the degradation to determine whether degradation of the integrated circuit is attributable to physical manipulation or an aging process.

6. The integrated circuit of claim 1, wherein the checking unit is further configured to store a history of determined information about the degradation of the integrated circuit, and to distinguish between abrupt changes in the history progressive changes.

7. The integrated circuit of claim 1, wherein the checking unit is further configured to attribute abrupt changes to damage and progressive changes to degradation.

8. The integrated circuit of claim 1, wherein the integrated circuit is digital.

9. The integrated circuit of claim 1, wherein the physical, unclonable function is implemented in digital form.

10. The integrated circuit of claim 1, wherein the integrated circuit comprises a plurality of integrity sensors provided in a distributed arrangement on a surface of the integrated circuit.

11. The integrated circuit of claim 10, wherein the checking unit is further configured to (a) compare response signals from different integrity sensors of the plurality of integrity sensors, (b) distinguish between a strong correlation and a weak correlation in the response signals, or (c) compare response signals from different integrity sensors of the plurality of integrity sensors and distinguish between a strong correlation and a weak correlation in the response signals.

12. The integrated circuit of claim 1, wherein the integrated circuit is reconfigurable, comprises reconfigurable components, or is reconfigurable and comprises reconfigurable components.

13. The integrated circuit of claim 1, wherein the integrity sensor is further configured to jointly use regular components of a main function of the integrated circuit.

14. The integrated circuit of claim 1, wherein the physical, unclonable function comprises at least one security fuse.

15. The integrated circuit of claim 1, wherein the physical, unclonable function comprises lines that run parallel or proximal to signal lines, and wherein the signal lines are not comprised by the physical, unclonable function.

16. The integrated circuit of claim 1, wherein the degradation of the integrated circuit is ascertainable by the integrity sensor through a comparison of the response signal with a reference response.

17. The integrated circuit of claim 1, wherein the integrated circuit is configured to implement a measure if the degradation exceeds a threshold value, wherein the measure is selected from the group consisting of provision of the first information about the degradation, temporary deactivation of the integrated circuit, permanent deactivation of the integrated circuit, deactivation of an affected partial functionality of the integrated circuit, activation of a restricted mode of operation of the integrated circuit, erasure of stored data, and combinations thereof.

18. The integrated circuit of claim 1, wherein the integrated circuit comprises a field programmable gate array.

19. The integrated circuit of claim 1, wherein the integrated circuit comprises an application-specific integrated circuit.

20. The integrated circuit of claim 13, wherein the regular components of the main function of the integrated circuit comprise data paths or clock paths.