DEVICE
First Claim
1. A device comprising:
- a first circuit; and
a second circuit,wherein the first circuit comprises a first memory,wherein the first memory is configured to store first data corresponding to a first address of a first instruction of the first circuit,wherein the second circuit comprises a second memory,wherein the second memory is configured to store second data to generate a signal for an operation test of the first circuit, and configured to store third data corresponding to a second address of a second instruction of the first circuit, andwherein the second circuit is configured to compare the third data and fourth data corresponding to a third address of a third instruction of the first circuit after the operation test.
1 Assignment
0 Petitions
Accused Products
Abstract
A device that is capable of generating a new test pattern after the design phase and has a small area of a circuit not in use during normal operation includes a first circuit and a second circuit. The second circuit includes a third circuit and fourth circuit. The fourth circuit has a function of storing data for determining the configuration of the third circuit. When a test for the operating state of the first circuit is performed, the second circuit has a function of generating a signal for the test. When the test is not performed, the second circuit has a function of storing data used for processing in the first circuit and a function of comparing a plurality of signals.
19 Citations
20 Claims
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1. A device comprising:
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a first circuit; and a second circuit, wherein the first circuit comprises a first memory, wherein the first memory is configured to store first data corresponding to a first address of a first instruction of the first circuit, wherein the second circuit comprises a second memory, wherein the second memory is configured to store second data to generate a signal for an operation test of the first circuit, and configured to store third data corresponding to a second address of a second instruction of the first circuit, and wherein the second circuit is configured to compare the third data and fourth data corresponding to a third address of a third instruction of the first circuit after the operation test. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A device comprising:
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a first circuit; and a second circuit, wherein the first circuit comprises a first memory, wherein the first memory is configured to store first data corresponding to a first address of a first instruction of the first circuit, wherein the second circuit comprises a second memory and a third memory, wherein the second memory is configured to store second data to generate a signal for an operation test of the first circuit, and configured to store third data corresponding to a second address of a second instruction of the first circuit after the operation test, wherein the third memory is configured to store fourth data to generate the signal for the operation test of the first circuit, and configured to store inverted data of the third data after the operation test, and wherein the second circuit is configured to compare the third data and fifth data corresponding to a third address of a third instruction of the first circuit after the operation test. - View Dependent Claims (8, 9, 10, 11, 12, 13)
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14. A device comprising:
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a processor; and a programmable device, wherein the processor comprises a cache memory, wherein the cache memory is configured to store data corresponding to an address of a first instruction of the processor, wherein the programmable device comprises a first configuration memory, wherein the first configuration memory is configured to store first configuration data to generate a signal for an operation test of the processor, and configured to store data corresponding to an address of a second instruction of the processor, and wherein the programmable device is configured to compare the address of the second instruction of the processor and an address of a third instruction of the processor after the operation test. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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Specification