MEMORY CONTROLLER AND MEMORY SYSTEM

• US 20150193301A1
• Filed: 08/27/2014
• Published: 07/09/2015
• Est. Priority Date: 01/06/2014
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Sukegawa, Hiroshi, Yao, Hiroshi, Takeda, Naomi
• Application Number:
  US14/469,754
• Publication Number:
  US 20150193301A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 2029/4402 Internal storage of test result, quality data, chip identification, repair information
• CPC Class Codes: G11C 29/08 Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing

Abstract

A controller according to one embodiment controls a memory, the memory including blocks and configured to erase data in the blocks with each of the blocks as a minimum unit. Each of the blocks includes unit memory areas each specified by an address. The controller is configured to add a code for error correction to received data to generate a data unit, divide the data unit into data unit sections, and write the data unit sections in unit memory areas of respective blocks, the unit memory areas having different addresses.

Claims

1. A controller which controls a memory, wherein

the memory comprises blocks and is configured to erase data in the blocks with each of the blocks as a minimum unit,

each of the blocks comprises unit memory areas each specified by an address,

the controller is configured to:

add a code for error correction to received data to generate a data unit;

divide the data unit into data unit sections, and

write the data unit sections in unit memory areas of respective blocks, the unit memory areas having different addresses.

2. The controller of claim 1, wherein

each of the blocks comprises word lines each having an address unique within that block,

each of the word lines specifies a physical unit comprising memory cells coupled to that word line, and

each of the unit memory areas comprises at least a physical unit.

3. The controller of claim 2, wherein

the memory has a substrate,

the physical units are formed above the substrate, and

physical units having the same address in respective blocks are located at the same height from the substrate.

4. The controller of claim 1, wherein

the controller is further configured to:

generate data units in parallel, and

write respective data unit sections of the data units in the blocks in parallel.

5. The controller of claim 1, wherein

the controller is further configured to write data unit sections of a data unit in the blocks in parallel.

6. The controller of claim 1, wherein

the controller is further configured to:

use blocks having the same address as a management unit, and

erase all data items in a management unit after that management unit becomes to include only invalid data items not included in a valid data unit.

7. A controller which controls memories, wherein

each of the memories comprises unit memory areas each specified by an address,

the controller is configured to:

add a code for error correction to received data to generate a data unit;

divide the data unit into data unit sections, and

write the data unit sections in unit memory areas of respective memories, the unit memory areas having different addresses.

8. The controller of claim 7, wherein

each of the memories comprises blocks,

each of the blocks comprises word lines each having an address unique within that block,

each of the blocks comprises word lines each having a unique address within that block,

each of the word lines specifies a physical unit comprising memory cells coupled to that word line, and

each of the unit memory areas comprises at least a physical unit.

9. The controller of claim 7, wherein

the memories have respective substrates,

the physical units are formed above a corresponding one of the substrates, and

physical units having the same address in respective memories are located at the same height from respective substrates.

10. The controller of claim 7, wherein

the controller is further configured to:

generate data units in parallel, and

write respective data unit sections of the data units in the memories in parallel.

11. The controller of claim 7, wherein

the controller is further configured to write data unit sections of a data unit in the memories in parallel.

12. The controller of claim 7, wherein

each of the memories comprises blocks and is further configured to erase data in the blocks with each of the blocks as a minimum unit,

the controller is further configured to:

use respective blocks of the memories having the same address as a management unit, and

erase all data items in a management unit after that management unit becomes to include only invalid data items not included in a valid data unit.

13. A memory system comprising:

memories each comprising unit memory areas each specified by an address; and

a controller configured to;

add a code for error correction to received data to generate a data unit;

divide the data unit into data unit sections, and

write the data unit sections in unit memory areas of respective memories, the unit memory areas having different addresses.

14. The system of claim 13, wherein

each of the memories comprises blocks,

each of the blocks comprises word lines each having an address unique within that block,

each of the blocks comprises word lines each having a unique address within that block,

each of the word lines specifies a physical unit comprising memory cells coupled to that word line, and

each of the unit memory areas comprises at least a physical unit.

15. The system of claim 14, wherein

the memories have respective substrates,

the physical units are formed above a corresponding one of the substrates, and

physical units having the same address in respective memories are located at the same height from respective substrates.

16. The system of claim 13, wherein

the controller is further configured to:

generate data units in parallel, and

write respective data unit sections of the data units in the memories in parallel.

17. The system of claim 13, wherein

the controller is further configured to write data unit sections of a data unit in the memories in parallel.

18. The system of claim 13, wherein

each of the memories comprises blocks and is further configured to erase data in the blocks with each of the blocks as a minimum unit,

the controller is further configured to:

use respective blocks of the memories having the same address as a management unit, and

erase all data items in a management unit after that management unit becomes to include only invalid data items not included in a valid data unit.