LIQUID CRYSTAL DISPLAY AND METHOD FOR DRIVING THE SAME

• US 20150194110A1
• Filed: 11/05/2014
• Published: 07/09/2015
• Est. Priority Date: 01/08/2014
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: PARK, Su-Hyeong, SEO, Ji-Myoung, JUNG, Ho-Yong, LEE, Eun-Ho, PARK, Cheol-Woo
• Granted Patent: US 9,824,653 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G09G 2310/0224 Details of interlacing
• CPC Class Codes: G09G 2310/0264 Details of driving circuits
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 3/3607 for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels display of colours in flat matrix panels other than liquid crystal displays G09G3/2003; grey scales specific for television H04N3/127
• CPC Class Codes: G09G 3/3614 Control of polarity reversal in general
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G09G 3/3688 suitable for active matrices only

Abstract

A liquid crystal display includes: a display panel including data lines, scan lines and a plurality of pixels connected to the data lines and the scan lines; a scan driver configured to supply scan signals to the scan lines; a data driver configured to supply data voltages to the data lines; and a timing controller configured to control operation timings of the scan driver and the data driver, where the timing controller is configured to output a plurality of scan output enable signals to the scan driver, and the scan driver is configured to supply odd scan signals to odd scan lines based on a first scan output enable signal of the scan output enable signals and to supply even scan signals to even scan lines based on a second scan output enable signal of the scan output enable signals.

Claims

1. A liquid crystal display, comprising:

a display panel comprising data lines, scan lines, and a plurality of pixels connected to the data lines and the scan lines;

a scan driver configured to supply scan signals to the scan lines;

a data driver configured to supply data voltages to the data lines; and

a timing controller configured to control operation timings of the scan driver and the data driver,

wherein the timing controller is configured to output a plurality of scan output enable signals to the scan driver,

wherein the scan driver is configured to supply odd scan signals to odd scan lines based on a first scan output enable signal of the scan output enable signals, and to supply even scan signals to even scan lines based on a second scan output enable signal of the scan output enable signals.

2. The liquid crystal display of claim 1, wherein

a phase of the first scan output enable signal is different from a phase of the second scan output enable signal, or

the second scan output enable signal is a signal delayed from the first scan output enable signal.

3. The liquid crystal display of claim 1, wherein

the scan driver is configured to sequentially supply the scan signals to the scan lines in a sequential addressing mode and to supply the scan signals to the scan lines in a predetermined order in a transition minimization addressing mode.

4. The liquid crystal display of claim 3, wherein the timing controller is configured to output a scan start signal and a scan clock signal to the scan driver.

5. The liquid crystal display of claim 4, wherein phases of the first and second scan output enable signals in the sequential addressing mode is different from phases of the first and second scan output enable signals in the transition minimization addressing mode.

6. The liquid crystal display of claim 5, wherein the scan driver comprises:

a D flip-flop circuit configured to sequentially output pulse signals based on the scan clock signal in response to the scan start signal;

odd AND gates coupled to the odd scan lines, wherein the odd AND gates are configured to output a result of AND operation for an inversion signal of the first scan output enable signal and the pulse signals from the D flip-flop circuit, and; and

even AND gates coupled to the even scan lines, wherein the even AND gates are configured to output a result of AND operation for an inversion signal of the second scan output enable signal and the pulse signals from the D flip-flop circuit.

7. The liquid crystal display of claim 4, wherein the scan driver is configured

to supply scan signals to (4u−

3)-th scan lines based on the first scan output enable signal,

to supply scan signals to (4u−

2)-th scan lines based on the second scan output enable signal,

to supply scan signals to (4u−

1)-th scan lines based on a third scan output enable signal of the scan output enable signals, and

to supply scan signals to (4u)-th scan lines based on a fourth scan output signal of the scan output enable signals,

wherein u is a natural number.

8. The liquid crystal display of claim 7, wherein

phases of the first to fourth scan output enable signals are different from each other, or

the first to fourth scan output enable signals are signals sequentially delayed from one another.

9. The liquid crystal display of claim 7, wherein phases of the first to fourth scan output enable signals in the sequential addressing mode are different from phases of the first to fourth scan output enable signals in the transition minimization addressing mode.

10. The liquid crystal display of claim 9, wherein the scan driver comprises:

a D flip-flop circuit configured to sequentially output pulse signals based on the scan clock signal in response to the scan start signal;

(4u−

3)-th AND gates coupled to the (4u−

3)-th scan lines, wherein the (4u−

3)-th AND gates are configured to output a result of AND operation for an inversion signal of the first scan output enable signal and the pulse signals from the D flip-flop circuit;

(4u−

2)-th AND gates coupled to the (4u−

2)-th scan lines, wherein the (4u−

2)-th AND gates are configured to output a result of AND operation for an inversion signal of the second scan output enable signal and the pulse signals from the D flip-flop circuit;

(4u−

1)-th AND gates coupled to the (4u−

1)-th scan lines, wherein the (4u−

1)-th AND gates are configured to output a result of AND operation for an inversion signal of the third scan output enable signal and the pulse signals from the D flip-flop circuit; and

(4u)-th AND gates coupled to the (4u−

2)-th scan lines, wherein the (4u−

2)-th AND gates are configured to output a result of AND operation for an inversion signal of the fourth scan output enable signal and the pulse signals from the D flip-flop circuit.

11. The liquid crystal display of claim 5, wherein the scan driver comprises:

a first scan drive circuit configured to receive the scan start signal, the scan clock signal and the first scan output enable signal; and

a second scan drive circuit configured to receive the scan start signal, the scan clock signal and the second scan output enable signal.

12. The liquid crystal display of claim 11, wherein the first scan drive circuit comprises:

a first D flip-flop circuit configured to sequentially output pulse signals based on the scan clock signal in response to the scan start signal; and

a first AND gate group coupled to the odd scan lines, wherein the first AND gate group is configured to output a result of AND operation for an inversion signal of the first scan output enable signal and the pulse signals from the first D flip-flop circuit.

13. The liquid crystal display of claim 12, wherein the second scan drive circuit comprises:

a second D flip-flop circuit configured to sequentially output pulse signals according to the scan clock signal in response to the scan start signal; and

a second AND gate group coupled to the even scan lines, wherein the second AND gate group is configured to output a result of AND operation for an inversion signal of the second scan output enable signal and the pulse signals from the second D flip-flop circuit.

14. The liquid crystal display of claim 9, wherein the scan driver comprises:

a first scan drive circuit configured to receive the scan start signal, the scan clock signal, and the first and third scan output enable signals; and

a second scan drive circuit configured to receive the scan start signal, the scan clock signal, and the second and fourth scan output enable signal.

15. The liquid crystal display of claim 14, wherein the first scan drive circuit comprises:

a first D flip-flop circuit configured to sequentially output pulse signals according to the scan clock signal in response to the scan start signal; and

a first AND gate group comprising;

odd AND gates coupled to the (4u−

3)-th scan lines, wherein the odd AND gates of the first AND gate group are configured to output a result of AND operation for an inversion signal of the first scan output enable signal and the pulse signals from the first D flip-flop circuit; and

even AND gates coupled to the (4u−

1)-th scan lines, wherein the even AND gates of the first AND gate group are configured to output a result of AND operation for an inversion signal of the third scan output enable signal and the pulse signals from the first D flip-flop circuit.

16. The liquid crystal display of claim 15, wherein the second scan drive circuit comprises:

a second D flip-flop circuit configured to sequentially output pulse signals according to the scan clock signal in response to the scan start signal; and

a second AND gate group comprising;

odd AND gates coupled to the (4u−

2)-th scan lines, wherein the odd AND gates of the second AND gate group are configured to output a result of AND operation for an inversion signal of the second scan output enable signal and the pulse signals from the second D flip-flop circuit; and

even AND gates coupled to the (4u)-th scan lines, wherein the even AND gates of the second AND gate group are configured to output a result of AND operation for an inversion signal of the fourth scan output enable signal and the pulse signals from the second D flip-flop circuit.

17. A method for driving a liquid crystal display, the method comprising:

outputting a plurality of scan output enable signals from a timing controller of the liquid crystal display to a scan driver of the liquid crystal display, wherein the timing controller controls the scan driver and a data driver of the liquid crystal display;

supplying scan signals from the scan driver to scan lines of a display panel of the liquid crystal display; and

supplying data voltages from the data driver to data lines of the display panel of the liquid crystal display,

wherein the supplying the scan signals from the scan driver to the scan lines comprises;

supplying the scan signals from the scan driver to odd scan lines based on a first scan output enable signal of the scan output enable signals; and

supplying the scan signals from the scan driver to even scan lines based on a second scan output enable signal of the scan output enable signals.

18. A liquid crystal display, comprising:

a display panel comprising data lines, scan lines, and a plurality of pixels connected to the data lines and the scan lines;

a scan driver configured to supply scan signals to the scan lines;

a data driver configured to supply data voltages to the data lines; and

a timing controller configured to control operation timings of the scan driver and the data driver,

wherein the timing controller is configured to output a scan output enable signal and a plurality of address signals,

wherein the scan driver is configured to output the scan signals to the scan lines based on the scan output enable signal and the address signals.

19. The liquid crystal display of claim 18, wherein

the phases of the address signals are different from each other, or

the address signals are signals sequentially delayed from each other.

20. A method for driving a liquid crystal display, the method comprising:

outputting a scan output enable signal and a plurality of address signals from a timing controller of the liquid crystal display to a scan driver of the liquid crystal display, wherein the timing controller controls the scan driver and a data driver of the liquid crystal display;

supplying scan signals from the scan driver to scan lines of a display panel of the liquid crystal display; and

supplying data voltages from the data driver to data lines of the display panel of the liquid crystal display,

wherein the supplying the scan signals from the scan driver to the scan lines comprises supplying the scan signals from the gate driver to the scan lines based on the scan output enable signal and the address signals.